The Archaeology of Fish Haul Creek, Hilton Head Island, Beaufort County, South Carolina: A Preliminary Statement and Recommendations

In May 1982 a potentially significant prehistoric archaeological site was identified on the northern end of Hilton Head Island by developer John Crago and his foreman, Jerre Wekhorst. This site, situated on the north edge of the Coggin and Fish Haul Creek marsh, was uncovered during the early stages of road construction in the Fish Haul subdivision (Baygall area of Hilton Head Island). Wekhorst collected abundant pottery as the work continued in the subdivision and took a small sample to the Charleston Museum, where we examined it for the first time in early June. This collection was notable not only for the mix of pottery (both Early and Middle Woodland period sherds were present), but also for the large size of the Early Woodland sherds

„No name, no business, no Precious, nothing. Only empty.“ J. R. R. Tolkien: Ein Autor der literarischen Moderne

Die vorliegende Arbeit behandelt das Problem der literarhistorischen Zuordnung J. R. R. Tolkiens in die literarische Strömung des Modernismus. Da Tolkien bis zum heutigen Zeitpunkt von der Literaturwissenschaft vor allem als Kinder-, Jugend- oder Fantaysautor, von der Tolkienforschung hingegen unter anderem als mediävistischer Autor gesehen wird, stellt die vorliegende Arbeit diese Sichtweisen in Frage

Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits

The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours

High level behavioural modelling of boundary scan architecture.

This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure