16,180 research outputs found
Urban and extra-urban hybrid vehicles: a technological review
Pollution derived from transportation systems is a worldwide, timelier issue than ever. The abatement actions of harmful substances in the air are on the agenda and they are necessary today to safeguard our welfare and that of the planet. Environmental pollution in large cities is approximately 20% due to the transportation system. In addition, private traffic contributes greatly to city pollution. Further, “vehicle operating life” is most often exceeded and vehicle emissions do not comply with European antipollution standards. It becomes mandatory to find a solution that respects the environment and, realize an appropriate transportation service to the customers. New technologies related to hybrid –electric engines are making great strides in reducing emissions, and the funds allocated by public authorities should be addressed. In addition, the use
(implementation) of new technologies is also convenient from an economic point of view. In fact, by implementing the use of hybrid vehicles, fuel consumption can be reduced. The different hybrid configurations presented refer to such a series architecture, developed by the researchers and Research and Development groups. Regarding energy flows, different strategy logic or vehicle management units have been illustrated. Various configurations and vehicles were studied by simulating different driving cycles, both European approval and homologation and customer ones (typically municipal and university). The simulations have provided guidance on the optimal proposed configuration and information on the component to be used
Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK
This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI
Output Filter Aware Optimization of the Noise Shaping Properties of {\Delta}{\Sigma} Modulators via Semi-Definite Programming
The Noise Transfer Function (NTF) of {\Delta}{\Sigma} modulators is typically
designed after the features of the input signal. We suggest that in many
applications, and notably those involving D/D and D/A conversion or actuation,
the NTF should instead be shaped after the properties of the
output/reconstruction filter. To this aim, we propose a framework for optimal
design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite
programming. Some examples illustrate how in practical cases the proposed
strategy can outperform more standard approaches.Comment: 14 pages, 18 figures, journal. Code accompanying the paper is
available at http://pydsm.googlecode.co
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration
We empirically evaluate an undervolting technique, i.e., underscaling the
circuit supply voltage below the nominal level, to improve the power-efficiency
of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable
Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing
faults due to excessive circuit latency increase. We evaluate the
reliability-power trade-off for such accelerators. Specifically, we
experimentally study the reduced-voltage operation of multiple components of
real FPGAs, characterize the corresponding reliability behavior of CNN
accelerators, propose techniques to minimize the drawbacks of reduced-voltage
operation, and combine undervolting with architectural CNN optimization
techniques, i.e., quantization and pruning. We investigate the effect of
environmental temperature on the reliability-power trade-off of such
accelerators. We perform experiments on three identical samples of modern
Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification
CNN benchmarks. This approach allows us to study the effects of our
undervolting technique for both software and hardware variability. We achieve
more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain
is the result of eliminating the voltage guardband region, i.e., the safe
voltage region below the nominal level that is set by FPGA vendor to ensure
correct functionality in worst-case environmental and circuit conditions. 43%
of the power-efficiency gain is due to further undervolting below the
guardband, which comes at the cost of accuracy loss in the CNN accelerator. We
evaluate an effective frequency underscaling technique that prevents this
accuracy loss, and find that it reduces the power-efficiency gain from 43% to
25%.Comment: To appear at the DSN 2020 conferenc
Novel Front-end Electronics for Time Projection Chamber Detectors
Este trabajo ha sido realizado en la Organización Europea para la Investigación Nuclear (CERN) y forma parte del proyecto de investigación Europeo para futuros aceleradores lineales (EUDET).
En física de partículas existen diferentes categorías de detectores de partículas. El diseño presentado esta centrado en un tipo particular de detector de trayectoria de partículas denominado TPC (Time Projection Chamber) que proporciona una imagen en tres dimensiones de las partículas eléctricamente cargadas que atraviesan su volumen gaseoso.
La tesis incluye un estudio de los objetivos para futuros detectores, resumiendo los parámetros que un sistema de adquisición de datos debe cumplir en esos casos. Además, estos requisitos son comparados con los actuales sistemas de lectura utilizados en diferentes detectores TPC. Se concluye que ninguno de los sistemas cumple las restrictivas condiciones. Algunos de los principales objetivos para futuros detectores TPC son un altísimo nivel de integración, incremento del número de canales, electrónica más rápida y muy baja potencia.
El principal inconveniente del estado del arte de los sistemas anteriores es la utilización de varios circuitos integrados en la cadena de adquisición. Este hecho hace imposible alcanzar el altísimo nivel de integración requerido para futuros detectores. Además, un aumento del número de canales y frecuencia de muestreo haría incrementar hasta valores no permitidos la potencia utilizada. Y en consecuencia, incrementar la refrigeración necesaria (en caso de ser posible).
Una de las novedades presentadas es la integración de toda la cadena de adquisición (filtros analógicos de entrada, conversor analógico-digital (ADC) y procesado de señal digital) en un único circuito integrado en tecnología de 130nm. Este chip es el primero que realiza esta altísima integración para detectores TPC.
Por otro lado, se presenta un análisis detallado de los filtros de procesado de señal. Los objetivos más importantes es la reduccióGarcía García, EJ. (2012). Novel Front-end Electronics for Time Projection Chamber Detectors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16980Palanci
JUNO Conceptual Design Report
The Jiangmen Underground Neutrino Observatory (JUNO) is proposed to determine
the neutrino mass hierarchy using an underground liquid scintillator detector.
It is located 53 km away from both Yangjiang and Taishan Nuclear Power Plants
in Guangdong, China. The experimental hall, spanning more than 50 meters, is
under a granite mountain of over 700 m overburden. Within six years of running,
the detection of reactor antineutrinos can resolve the neutrino mass hierarchy
at a confidence level of 3-4, and determine neutrino oscillation
parameters , , and to
an accuracy of better than 1%. The JUNO detector can be also used to study
terrestrial and extra-terrestrial neutrinos and new physics beyond the Standard
Model. The central detector contains 20,000 tons liquid scintillator with an
acrylic sphere of 35 m in diameter. 17,000 508-mm diameter PMTs with high
quantum efficiency provide 75% optical coverage. The current choice of
the liquid scintillator is: linear alkyl benzene (LAB) as the solvent, plus PPO
as the scintillation fluor and a wavelength-shifter (Bis-MSB). The number of
detected photoelectrons per MeV is larger than 1,100 and the energy resolution
is expected to be 3% at 1 MeV. The calibration system is designed to deploy
multiple sources to cover the entire energy range of reactor antineutrinos, and
to achieve a full-volume position coverage inside the detector. The veto system
is used for muon detection, muon induced background study and reduction. It
consists of a Water Cherenkov detector and a Top Tracker system. The readout
system, the detector control system and the offline system insure efficient and
stable data acquisition and processing.Comment: 328 pages, 211 figure
Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals
Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve
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