Work in Progress: A Virtual Educational Robotics Coding Club Framework to Improve K-6 Students Emotional Engagement in STEM

The growing popularity and deployment of Internet of Things (IoT) devices has led to serious security concerns. The integration of a security operations center (SOC) becomes increasingly important in this situation to ensure the security of IoT devices. In this article, we will present a summary of IoT device security issues, their vulnerabilities, a review of current challenges to keep these devices secure, and discuss the role that SOC can bring in protecting IoT devices while considering the challenges encountered and the directions to consider when implementing a reliable SOC for IoT monitoring

The Role of SOC in Ensuring the Security of IoT Devices: A Review of Current Challenges and Future Directions

The growing popularity and deployment of Internet of Things (IoT) devices has led to serious security concerns. The integration of a security operations center (SOC) becomes increasingly important in this situation to ensure the security of IoT devices. In this article, we will present a summary of IoT device security issues, their vulnerabilities, a review of current challenges to keep these devices secure, and discuss the role that SOC can bring in protecting IoT devices while considering the challenges encountered and the directions to consider when implementing a reliable SOC for IoT monitoring

Low Power Design Techniques And Its Implementation On Direct Memory Access (DMA)

As the number of transistors in a SoC has been increasing rapidly, the integration complexity has increased as well. Besides complexity, IC designers also faced some other challenges including maintaining the power, performance and area of an IC. Bilangan transistor dalam SoC yang meningkat secara mendadak telah menyebabkan kerumitan integrasi turut meningkat pada masa yang sama. Selain kerumitan integrasi, pereka IC juga menghadapi beberapa cabaran termasuk untuk mengekalkan kuasa, prestasi dan keluasan IC

Comparative Study of Various Systems on Chips Embedded in Mobile Devices

Systems-on-chips (SoCs) are the latest incarnation of very large scale integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors. Harnessing all this computing power requires designers to move beyond logic design into computer architecture, meet real-time deadlines, ensure low-power operation, and so on. These opportunities and challenges make SoC design an important field of research. So in the paper we will try to focus on the various aspects of SOC and the applications offered by it. Also the different parameters to be checked for functional verification like integration and complexity are described in brief. We will focus mainly on the applications of system on chip in mobile devices and then we will compare various mobile vendors in terms of different parameters like cost, memory, features, weight, and battery life, audio and video applications. A brief discussion on the upcoming technologies in SoC used in smart phones as announced by Intel, Microsoft, Texas etc. is also taken up. Keywords: System on Chip, Core Frame Architecture, Arm Processors, Smartphone

Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements

Extensive research efforts are being carried out to evaluate and improve the reliability of computing devices either through beam experiments or simulation-based fault injection. Unfortunately, it is still largely unclear to which extend fault injection can provide an accurate error rate estimation at early stages and if beam experiments can be used to identify the weakest resources in a device. The importance and challenges associated with a timely, but yet realistic reliability evaluation grow with the increase of complexity in both the hardware domain, with the integration of different types of cores in an SoC (System-on-Chip), and the software domain, with the OS (operating system) required to take full advantage of the available resources. In this paper, we combine and analyze data gathered with extensive beam experiments (on the final physical CPU hardware) and microarchitectural fault injections (on early microarchitectural CPU models). We target a standalone Arm Cortex-A5 CPU and an Arm Cortex-A9 CPU integrated into an SoC and evaluate their reliability in bare-metal and Linux-based configurations. Combining experimental data that covers more than 18 million years of device time with the result of more than 176,000 injections we find that both the SoC integration and the presence of the OS increase the system DUEs (Detected Unrecoverable Errors) rate (for different reasons) but do not significantly impact the SDCs (Silent Data Corruptions) rate which is solely attributed to the CPU core. Our reliability analysis demonstrates that even considering SoC integration and OS inclusion, early, pre-silicon microarchitecture-level fault injection delivers accurate SDC rates estimations and lower bounds for the DUE rates

Unlocking Hardware Security Assurance: The Potential of LLMs

System-on-Chips (SoCs) form the crux of modern computing systems. SoCs enable high-level integration through the utilization of multiple Intellectual Property (IP) cores. However, the integration of multiple IP cores also presents unique challenges owing to their inherent vulnerabilities, thereby compromising the security of the entire system. Hence, it is imperative to perform hardware security validation to address these concerns. The efficiency of this validation procedure is contingent on the quality of the SoC security properties provided. However, generating security properties with traditional approaches often requires expert intervention and is limited to a few IPs, thereby resulting in a time-consuming and non-robust process. To address this issue, we, for the first time, propose a novel and automated Natural Language Processing (NLP)-based Security Property Generator (NSPG). Specifically, our approach utilizes hardware documentation in order to propose the first hardware security-specific language model, HS-BERT, for extracting security properties dedicated to hardware design. To evaluate our proposed technique, we trained the HS-BERT model using sentences from RISC-V, OpenRISC, MIPS, OpenSPARC, and OpenTitan SoC documentation. When assessedb on five untrained OpenTitan hardware IP documents, NSPG was able to extract 326 security properties from 1723 sentences. This, in turn, aided in identifying eight security bugs in the OpenTitan SoC design presented in the hardware hacking competition, Hack@DAC 2022

Unified System on Chip RESTAPI Service (USOCRS)

Abstract. This thesis investigates the development of a Unified System on Chip RESTAPI Service (USOCRS) to enhance the efficiency and effectiveness of SOC verification reporting. The research aims to overcome the challenges associated with the transfer, utilization, and interpretation of SoC verification reports by creating a unified platform that integrates various tools and technologies. The research methodology used in this study follows a design science approach. A thorough literature review was conducted to explore existing approaches and technologies related to SOC verification reporting, automation, data visualization, and API development. The review revealed gaps in the current state of the field, providing a basis for further investigation. Using the insights gained from the literature review, a system design and implementation plan were developed. This plan makes use of cutting-edge technologies such as FASTAPI, SQL and NoSQL databases, Azure Active Directory for authentication, and Cloud services. The Verification Toolbox was employed to validate SoC reports based on the organization’s standards. The system went through manual testing, and user satisfaction was evaluated to ensure its functionality and usability. The results of this study demonstrate the successful design and implementation of the USOCRS, offering SOC engineers a unified and secure platform for uploading, validating, storing, and retrieving verification reports. The USOCRS facilitates seamless communication between users and the API, granting easy access to vital information including successes, failures, and test coverage derived from submitted SoC verification reports. By automating and standardizing the SOC verification reporting process, the USOCRS eliminates manual and repetitive tasks usually done by developers, thereby enhancing productivity, and establishing a robust and reliable framework for report storage and retrieval. Through the integration of diverse tools and technologies, the USOCRS presents a comprehensive solution that adheres to the required specifications of the SOC schema used within the organization. Furthermore, the USOCRS significantly improves the efficiency and effectiveness of SOC verification reporting. It facilitates the submission process, reduces latency through optimized data storage, and enables meaningful extraction and analysis of report data

A System-on-Chip solution for a low power active capsule endoscope with therapeutic capabilities for clip application in the gastrointestinal tract

This paper addresses the circuit implementation challenges resulting from the integration of a therapeutic clip in a magnetically maneuverable wireless capsule intended for colonoscopy. To deal with the size constraints typical of a capsule endoscope, an Application Specific Integrated Circuit (ASIC) has been designed specifically to habilitate the release of the therapeutic clip. The ASIC is a complete System on Chip (SoC) that incorporates a circuit for the low power release of the clip, thus overcoming the limitations of the power supply system. With a size of 14mm2, the ASIC can be incorporated in practically any capsule endoscope, consuming only an idle-state power of 1.5mW

Reliability project optimization : a South African rail case

Abstract: The delivery of projects in the rail industry is a challenge. Transnet SOC Ltd (The South African national rail entity) is the sole bulk freight logistics rail company in South Africa. Transnet Capital Projects (TCP), a division of Transnet SOC Ltd, acts as a service provider to all the operating divisions of Transnet. TCP projects constantly failed due to what seemed like project integration challenges. The purpose of this research is to determine Transnet’s deficiencies and recommend solutions based on project management best practice in the field of railway engineering. This was achieved through the use of a questionnaire that was designed based on the lessons learnt, via an international best practice review, specific to railway projects. The research found that the major deficiencies lay within various levels within Transnet, specific issues being people and other issues being structural and technological. The research recommends a change in the TCP organizational structure, the recruitment of rail experts, skills development of project managers, the introduction of new railway software and the establishment of an Enterprise Project Management Office as potential international best practice solutions

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems