Memcapacitive Devices in Logic and Crossbar Applications

Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and nonlinear characteristics have many benefits, reducing the energy consumption is limited by the resistive nature of the devices. Memcapacitors would address that limitation while still having all the benefits of memristors. Recent work has shown that with adjusted parameters during the fabrication process, a metal-oxide device can indeed exhibit a memcapacitive behavior. We introduce novel memcapacitive logic gates and memcapacitive crossbar classifiers as a proof of concept that such applications can outperform memristor-based architectures. The results illustrate that, compared to memristive logic gates, our memcapacitive gates consume about 7x less power. The memcapacitive crossbar classifier achieves similar classification performance but reduces the power consumption by a factor of about 1,500x for the MNIST dataset and a factor of about 1,000x for the CIFAR-10 dataset compared to a memristive crossbar. Our simulation results demonstrate that memcapacitive devices have great potential for both Boolean logic and analog low-power applications

Resistive switching RAM devices based on amorphous oxide semiconductors for system on panel applications

This work reports the mask design, fabrication and characterization of memristor devices with diode like electrical behavior at pristine state. It is due to the presence of Schottky junctions between Zinc-tin-oxide (ZTO) and platinum - Indium-galliumzinc- oxide (IGZO) and molybdenum oxide for two different Metal-Insulator-Metal (MIM) configurations. The devices were exclusively produced using physical vapor deposition processes without intentional heating. Typical advanced electrical analysis of ReRAM device was performed. The Pt-ZTO-TiAu devices showed pinched hysteresis properties with large Ron=of f ratio, fast switching which can be controlled in a digital SET and analog RESET operation. However, large device-to-device variations and stability are the main issues which is due to the processing. On the other hand, the Mo-IGZO-Mo devices showed a small Ron=of f ratio and only analog operation. There was a high yield and stability. However, using DC sweep for cycling led to a charging phenomenon. Using SET/RESET pulses, the devices sustain hundreds of cycles without deterioration or movement of the resistance states, showing great resilience and retention

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in-situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.Comment: This is a preprint of an article accepted for publication in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no. 2, June 201

Design and analysis of memristor-based reliable crossbar architectures

The conventional transistor-based computing landscape is already undergoing dramatic changes. While transistor-based devices’ scaling is approaching its physical limits in nanometer technologies, memristive technologies hold the potential to scale to much smaller geometries. Memristive devices are used majorly in memory design but they also have unignorable applications in logic design, neuromorphic computing, sensors among many others. The most critical research and development problems that must be resolved before memristive architectures become mainstream are related to their reliability. One of such reliability issue is the sneak-paths current which limits the maximum crossbar array size. This thesis presents various designs of the memristor based crossbar architecture and corresponding experimental analysis towards addressing its reliability issues. Novel contribution of this thesis starts with the formulation of robust analytic models for read and write schemes used in memristive crossbar arrays. These novel models are less restrictive and are suitable for accurate mathematical analysis of any mn crossbar array and the evaluation of their performance during these critical operations. In order to minimise the sneak-paths problem, we propose techniques and conditions for reliable read operations using simultaneous access of multiple bits in the crossbar array. Two new write techniques are also presented, one to minimise failure during single cell write and the other designed for multiple cells write operation. Experimental results prove that the single write technique minimises write voltage drop degradation compared to existing techniques. Test results from the multiple cells write technique show it consumes less power than other techniques depending on the chosen configuration. Lastly, a novel Verilog-A memristor model for simulation and analysis of memristor’s application in gas sensing is presented. This proposed model captures the gas sensing properties of titanium-dioxide using gas concentration to control the overall memristance of the device. This model is used to design and simulate a first-of-its-kind sneak-paths free memristor-based gas detection arrays. Experimental results from a 88 memristor sensor array show that there is a ten fold improvement in the accuracy of the sensor’s response when compared with a single memristor sensor

DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES

The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible

Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing

A Multi-Value 3D Crossbar Array Nonvolatile Memory Based on Pure Memristors

© 2022, The Author(s), under exclusive licence to EDP Sciences, Springer-Verlag GmbH Germany, part of Springer Nature. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1140/epjs/s11734-022-00576-9How to improve the storage density and solve the sneak path current problem has become the key to the design of nonvolatile memristive memory. In this paper, a high storage density and high reading/writing speed 3D crossbar array non-volatile memory based on pure memristors is proposed. The main works are as follows: (1) an extensible memristive cluster is proposed, (2) a memristive switch is designed, and (3) a 3D crossbar array non-volatile memory is constructed. The memory cell of the 3D crossbar array non-volatile memory is constructed by pure memristors and can be extended by adding memristor in a memristive cluster or adding memristive clusters in a memory cell to realize multi-value storage. The memristive switch can effectively reduce the sneak path current effect. The pure memristive memory cell solves the conflict between the storage density and sneak path current effect and greatly improves the storage density of memory cells. Furthermore, the 3D cross-array structure allows different memory cells on the same layer or different layers to be read and written in parallel, which greatly improves the speed of reading and writing. Simulations with PSpice verifies that the proposed memristive cluster can realize stable multi-value storage, has higher storage density, faster reading and writing speed, fewer input ports and output ports, better stability, and lower power consumption. Moreover, the structure proposed in this paper can also be used in the circuit design of the neuromorphic network, logic circuit, and other memristive circuits.Peer reviewe

Analogue auto-associative memory using a multi-valued memristive memory cell

Most brain-like computing systems build up from neural networks. While there are some essential problems with this approach, it is well-known that the brain functionally operates as an associative memory. Building associative memories using conventional CMOS technology has already been performed, but this approach suffers from a lack of scalability and information density. Additionally, for a long time, one of the differences between analogue and digital electronics was the fact that digital electronics allowed for easier data storage through a variety of different memory cell architectures. These memory designs make extensive use of transistors and generally trade area, performance and power. However, memristors can be used as high density, analogue, passive storage elements and this paper presents 2 memory cell designs that allow for such multi-valued storage. The noise resistance of these cells is tested and indicates a very good tolerance to external influences, while overall they provide for a very accurate storage of data with high information density. Following on from the description of the storage cells, the paper then continues to build them into an associative memory

Hierarchical Temporal Memory using Memristor Networks: A Survey

This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed

Applications of memristors in conventional analogue electronics

This dissertation presents the steps employed to activate and utilise analogue memristive devices in conventional analogue circuits and beyond. TiO2 memristors are mainly utilised in this study, and their large variability in operation in between similar devices is identified. A specialised memristor characterisation instrument is designed and built to mitigate this issue and to allow access to large numbers of devices at a time. Its performance is quantified against linear resistors, crossbars of linear resistors, stand-alone memristive elements and crossbars of memristors. This platform allows for a wide range of different pulsing algorithms to be applied on individual devices, or on crossbars of memristive elements, and is used throughout this dissertation. Different ways of achieving analogue resistive switching from any device state are presented. Results of these are used to devise a state-of-art biasing parameter finder which automatically extracts pulsing parameters that induce repeatable analogue resistive switching. IV measurements taken during analogue resistive switching are then utilised to model the internal atomic structure of two devices, via fittings by the Simmons tunnelling barrier model. These reveal that voltage pulses modulate a nano-tunnelling gap along a conical shape. Further retention measurements are performed which reveal that under certain conditions, TiO2 memristors become volatile at short time scales. This volatile behaviour is then implemented into a novel SPICE volatile memristor model. These characterisation methods of solid-state devices allowed for inclusion of TiO2 memristors in practical electronic circuits. Firstly, in the context of large analogue resistive crossbars, a crosspoint reading method is analysed and improved via a 3-step technique. Its scaling performance is then quantified via SPICE simulations. Next, the observed volatile dynamics of memristors are exploited in two separate sequence detectors, with applications in neuromorphic engineering. Finally, the memristor as a programmable resistive weight is exploited to synthesise a memristive programmable gain amplifier and a practical memristive automatic gain control circuit.Open Acces