Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Recently, there are increasing demands for fully flexible Bose Chaudhuri Hocquenghem (BCH) decoders, which can support different dimensions of Galois fields (GF) operations. As the previous BCH decoders are mainly targeting the fixed GF operations, the conventional techniques are no longer suitable for multiple GF dimensions. For the area-optimized flexible BCH decoders, in this paper, we present several optimization schemes for reducing hardware costs of multi-dimensional GF operations. In the proposed optimizations, we first reformulate the matrix operations in syndrome calculation and Chien search for sharing more common sub-expressions between GF operations having different dimensions. The cell based multi-m GF multiplier is newly introduced for the area-efficient flexible key-equation solver. As case studies, we design several prototype flexible BCH decoders for digital video broadcasting systems and NAND flash memory controllers managing different page sizes. The implementation results show that the proposed fully-flexible BCH decoder architecture remarkably enhances the area-efficiency compared with the conventional solutions.112Ysciescopu

Design and Optimization of Adaptable BCH Codecs for NAND Flash Memories

NAND flash memories represent a key storage technology for solid-state storage systems. However, they suffer from serious reliability and endurance issues that must be mitigated by the use of proper error correction codes. This paper proposes the design and implementation of an optimized Bose-Chaudhuri-Hocquenghem hardware codec core able to adapt its correction capability in a range of predefined values. Code adaptability makes it possible to efficiently trade-off, in-field reliability and code complexity. This feature is very important considering that the reliability of a NAND flash memory continuously decreases over time, meaning that the required correction capability is not fixed during the life of the device. Experimental results show that the proposed architecture enables to save resources when the device is in the early stages of its lifecycle, while introducing a limited overhead in terms of are

Area Reduction Of Syndrome Calculator For Strong Bose-Chaudhuri-Hocquenghem Decoder

Bose–Chaudhuri–Hocquenghem (BCH) codes have a widespread use to provide the error protection for multiple random errors in a binary code. BCH codes is commonly applied in various practical application such as advanced solid-state drives (SSDs), high-speed fiber optical communications system and wireless communication system. The operation in a BCH decoder can be summarized into 3 steps: 1) compute the syndromes from the received codeword; 2) computing the error locator polynomial; 3) locating the errors. This research project proposed an area efficient Syndrome Calculator block of the BCH (n=255, k=111, t=18) decoder. In the previous SC block architecture, all the odd-index syndromes need to be computed by direct calculation which consume more area. In the current proposed architecture, Galois field’s property is exploited to compute the odd-index syndromes by using power operation in order to save the area consumption. This architecture is better in terms of area compared with previous architecture. In conclusion, by computing the odd-index syndromes with power operation, 8% area saving is achieved without compromising the power consumption and its operating frequency

A Microprocessor based hybrid system for digital error correction

The design of a microprocessor based hybrid system for digital error correction is presented. It is shown that such a system allows for implementation of several cyclic codes at a variety of throughput rates providing variable degrees of error correction depending on current user requirements. The theoretical basis for encoding and decoding of binary BCH codes is reviewed. Design and implementation of system hardware and software are described. A method for injection of independent bit errors with controllable statistics into the system is developed, and its accuracy verified by computer simulation. This method of controllable error injection is used to test performance of the designed system. In analysis, these results demonstrate the flexibility of operation provided by the hybrid nature of the system. Finally, potential applications and modifications are presented to reinforce the wide applicability of the system described in this thesis

Dependability Assessment of NAND Flash-memory for Mission-critical Applications

It is a matter of fact that NAND flash memory devices are well established in consumer market. However, it is not true that the same architectures adopted in the consumer market are suitable for mission critical applications like space. In fact, USB flash drives, digital cameras, MP3 players are usually adopted to store "less significant" data which are not changing frequently (e.g., MP3s, pictures, etc.). Therefore, in spite of NAND flash's drawbacks, a modest complexity is usually needed in the logic of commercial flash drives. On the other hand, mission critical applications have different reliability requirements from commercial scenarios. Moreover, they are usually playing in a hostile environment (e.g., the space) which contributes to worsen all the issues. We aim at providing practical valuable guidelines, comparisons and tradeoffs among the huge number of dimensions of fault tolerant methodologies for NAND flash applied to critical environments. We hope that such guidelines will be useful for our ongoing research and for all the interested reader

A Flexible BCH decoder for Flash Memory Systems using Cascaded BCH codes

NAND ash memories are widely used in consumer electronics, such as tablets, personal computers, smartphones, and gaming systems. However, unlike other standard storage devices, these ash memories suffer from various random errors. In order to address these reliability issues, various error correction codes (ECC) are employed. Bose-Chaudhuri Hocquenghem (BCH) code is the most common ECC used to address the errors in modern ash memories. Because of the limitation of the realization of the BCH codes for more extensive error correction, the modern ash memory devices use Low-density parity-check (LDPC) codes for error correction scheme. The realization of the LDPC decoders have greater complexity than BCH decoders, so these ECC decoders are implemented within the ash memory device. This thesis analyzes the limitation imposed by the state of the art implementation of BCH decoders and proposes a cascaded BCH code to address these limitations. In order to support a variety of ash memory devices, there are three main challenges to be addressed for BCH decoders. First, the latency of the BCH decoders, in the case of no error scenario, should be less than 100us. Second, there should be flexibility in supporting different ECC block size; more precisely, the solution should be able to support 256, 512, 1024, and 2048 bytes of ECC block. Third, there should be flexibility in supporting different bit errors. A recent development with Graphical Processing Units (GPUs) has attracted many researchers to use GPUs for non-graphical implementation. These GPUs are used in many consumer electronics as part of the system on chip (SOC) configuration. In this thesis we studied the limitation imposed by different implementations (VLSI, GPU, and CPU) of BCH decoders, and we propose a cascaded BCH code implemented using a hybrid approach to overcome the limitations of the BCH codes. By splitting the implementation across VLSI and GPUs, we have shown in this thesis that this method can provide flexibility over the block size and the bit error to be corrected