Pareto Points in SRAM Design Using the Sleepy Stack Approach

Abstract. Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultra-low leakage SRAM design which we call "sleepy stack SRAM." Unlike the straightforward sleep approach, sleepy stack SRAM can retain logic state during sleep mode, which is crucial for a memory element. Compared to the best alternative we could find, a 6-T SRAM cell with high-Vth transistors, the sleepy stack SRAM cell with 2xVth at 110°C achieves, using 0.07µ technology models, more than 2.77X leakage power reduction at a cost of 16% delay increase and 113% area increase. Alternatively, by widening wordline transistors and transistors in the pull-down network, the sleepy stack SRAM cell can achieve 2.26X leakage reduction without increasing delay at a cost of a 125% area penalty

DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power

A Study On Power Reduction Techniques For Comparator Based On Body Biasing

The growth of portable electronic devices in consumer market has led to the innovation of low power design. Furthermore, the scaling down of CMOS process technology has increased the transistor density. As a result, the device has higher functionality but more power is consumed per area unit. Hence power reduction technique is being explored in electronic integrated circuit design. In flash analog to digital converter (ADC), comparator consumes the most power. In this dissertation, power reductions techniques such as sleepy transistor technique, stack transistor technique and body biasing technique are studied. A conventional comparator, comparator reduced VDD and comparator with super cut-off CMOS (SCCMOS) and sleepy stack are implanted using 0.13 μm CMOS process technology. Then, a low power comparator is proposed using body biasing technique, sleepy stack transistor and super cut-off CMOS. Forward body biasing technique is used to decrease the threshold voltage. As a result, VDD is able to reduce. Hence, dynamic power consumption also reduced. Meanwhile, SCCMOS and sleepy stack transistor are used to reduce leakage current. As a consequence, the static power is reduced. From pre-layout simulation of proposed comparator, the static power is 94.66 pW compared to 404.2 μW for conventional comparator. Meanwhile, the dynamic power for proposed comparator is 14.76 μW compared 1.127 mV for conventional comparator. The pre-layout xiv simulation and post-layout simulation show there is no significant parasitic effect on the performance of proposed comparator

Review Paper on Power Efficient Hybrid D- Flip Flop

ABSTRACT: In nanometer CMOS technologies leakage powerhas become a serious concern and is a very important issue in hardware and software VLSI design. The leakage powerincreases as technology is scaled down. Low power flip-flops play a vital role for the design of low-power digital systems. In thispaper several different flip flop topologies are analyzed andpower efficient flip flop method is proposed. This paper presentssurvey on low power hybrid dual dynamic flip flop (DDFF) andembedded logic module (DDFF-ELM) based on DDFF. Thissurvey concludes that ultra low leakage CMOS structure calledas sleepy stack inverter pair method which is efficient in leakagepower reduction for design of low power hybrid flip flop thusproviding circuit designer with new choice to handle leakagepower problem

Implementation of dual stack technique for reducing leakage and dynamic power

This paper deals with proposal of a new dual stack approach for reducing both leakage and dynamic powers. The development of digital integrated circuits is challenged by higher power consumption. Thecombination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality ona chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become anincreasingly important issue in processor hardware and software design. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The leakage power increases astechnology is scaled down. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product whencompared to the existing methods. All well known approach is “Sleep” in this method we reduce leakage power. The proposed Dual Stack approach we reduce more power leakage. Dual Stack approach uses theadvantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the Dual Stack portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.The dual stack approach shows the least speed power product among all methods. The Dual Stack technique provides new ways to designers who require ultra-low leakage power consumption with much less speedpower product

FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPROACH IN CMOS BASED CIRCUIT DESIGNING

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation

Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications

AbstractThe leakage power dissipation has become one of the most challenging issues in low power VLSI circuit designs especially with on-chip devices as it doubles for every two years[4]-[5]. The scaling down of threshold voltage has contributed enormously towards increase in subthreshold leakage current thereby making the static (leakage) power dissipation very high. According to International Technology Roadmap for Semiconductors (ITRS), the total power dissipation may be significantly contributed by leakage power dissipation [1]. The battery operated devices with long duration in standby mode may be drained out very quickly due to the leakage power. In CMOS submicron technologies, leakage power dissipation plays a significant role. However, various low power design techniques for efficient minimization of leakage power are proposed in the literature review. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper. The present research study and its corresponding analysis are mainly focusing on circuit performance parameters. It is implied from the current literature that only an appropriate choice of leakage power minimization technique for a specific application can be effectively carried by a VLSI circuit designer based on sequential analytical approach

A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design

A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of low threshold voltage. For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers. According to ITRS (International technology road-map for semiconductors), leakage power is becoming a dominant part of total power consumption. To prolong the battery life of portable devices, leakage power reduction is the primary goal. The main objective of this paper is to present the analysis of leakage components, comprehensive study & analysis of leakage components and to present different proposed leakage power reduction techniques. DOI: 10.17762/ijritcc2321-8169.15022