Undersampling bandpass modulator architectures

Continuous-time delta sigma modulators -- Undersampling Delta-sigma modulators for radio receivers -- A novel continuous-time delta sigma modulator -- New delta modulator based on undersampling

Optical sampling and metrology using a soliton-effect compression pulse source

A low jitter optical pulse source for applications including optical sampling and optical metrology was modelled and then experimentally implemented using photonic components. Dispersion and non-linear fibre effects were utilised to compress a periodic optical waveform to generate pulses of the order of 10 picoseconds duration, via soliton-effect compression. Attractive features of this pulse source include electronically tuneable repetition rates greater than 1.5 GHz, ultra-short pulse duration (10-15 ps), and low timing jitter as measured by both harmonic analysis and single-sideband (SSB) phase noise measurements. The experimental implementation of the modelled compression scheme is discussed, including the successful removal of stimulated Brillouin scattering (SBS) through linewidth broadening by injection dithering or phase modulation. Timing jitter analysis identifies many unwanted artefacts generated by the SBS suppression methods, hence an experimental arrangement is devised (and was subsequently patented) which ensures that there are no phase modulation spikes present on the SSB phase noise spectrum over the offset range of interest for optical sampling applications, 10Hz-Nyquist. It is believed that this is the first detailed timing jitter study of a soliton-effect compression scheme. The soliton-effect compression pulses are then used to perform what is believed to be the first demonstration of optical sampling using this type of pulse source. The pulse source was also optimised for use in a novel optical metrology (range finding) system, which is being developed and patented under European Space Agency funding as an enabling technology for formation flying satellite missions. This new approach to optical metrology, known as Scanning Interferometric Pulse Overlap Detection (SIPOD), is based on scanning the optical pulse repetition rate to find the specific frequencies which allow the return pulses from the outlying satellite, i.e. the measurement arm, to overlap exactly with a reference pulse set on the hub satellite. By superimposing a low frequency phase modulation onto the optical pulse train, it is possible to detect the pulse overlap condition using conventional heterodyne detection. By rapidly scanning the pulse repetition rate to find two frequencies which provide the overlapping pulse condition, high precision optical pulses can be used to provide high resolution unambiguous range information, using only relatively simple electronic detection circuitry. SIPOD’s maximum longitudinal range measurement is limited only by the coherence length of the laser, which can be many tens of kilometres. Range measurements have been made to better than 10 microns resolution over extended duration trial periods, at measurement update rates of up to 470 Hz. This system is currently scheduled to fly on ESA’s PROBA-3 mission in 2012 to measure the intersatellite spacing for a two satellite coronagraph instrument. In summary, this thesis is believed to present three novel areas of research: the first detailed jitter characterisation of a soliton-effect compression source, the first optical sampling using such a compression source, and a novel optical metrology range finding system, known as SIPOD, which utilises the tuneable repetition rate and highly stable nature of the compression source pulses

Collective Pulse Dynamics: A New Timing Circuit Strategy

This work presents a novel CMOS behavior of self stabilization of ring oscillators using collective dynamics. It shows that phase error correction can occur in ring oscillators over multiple cycles without an external reference via the collective dynamics of pulses. In time domain this shows up as timing stability improvement in oscillators. Different timing stability metrics were analyzed to determine the correct methodology to analyze this stability improvement. Behavioral models were made to capture the effects of local dynamics and its collective effects. These models were shown to have a good correlation with the HSPICE circuit simulations and measured values. Multiple oscillator topologies and architectures were fabricated to test the model, behavior and subsequent analysis. Different pulse amplifier based ring oscillators show trends similar to that predicted by simulations and empirical relationships developed using behavioral simulations. Further transmission line stabilized traveling wave version of the pulse oscillators show a higher stability improvement. This work opens up a new design space in the timing circuits design where all the other conventional tricks are still applicable. It also opens up an application space due to the timing stability improvement in the order of 1000 cycles where conventional ADC’s and TDC’s work. Finally this work eases up the constraints of loop filter and source phase noise when oscillators are operated in a phase locked loop

A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 291-305).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Direct analog-to-digital conversion of multi-GHz radio frequency (RF) signals is the ultimate goal in software radio receiver design but remains a daunting challenge for any technology. This thesis examines the potential of superconducting technology for realizing RF analog-to-digital converters (ADCs) with improved performance. A bandpass delta-sigma (AE) modulator is an attractive architecture for digitizing narrowband signals with high linearity and a large signal-to-noise ratio (SNR). The design of a superconducting bandpass AE modulator presented here exploits several advantages of superconducting electronics: the high quality factor of resonators, the high sampling rates of comparators realized with Josephson junctions, natural quantization of voltage pulses, and high circuit sensitivity. Demonstration of a superconducting circuit operating at clock rates in the tens of GHz is often hindered by the difficulty of high speed interfacing with room-temperature test equipment. In this work, a test chip with integrated acquisition memory is used to simplify high speed testing in a cryogenic environment. The small size (256 bits) of the on-chip memory severely limits the frequency resolution of spectra based on standard fast Fourier transforms. Higher resolution spectra are obtained by "segmented correlation", a new method for testing ADCs. Two different techniques have been found for clocking the superconducting modulator at frequencies in the tens of GHz. In the first approach, an optical clocking technique was developed, in which picosecond laser pulses are delivered via optical fiber to an on-chip metal-semiconductor-metal (MSM) photodiode, whose output current pulses trigger the Josephson circuitry. In the second approach, the superconducting modulator is clocked by an on-chip Josephson oscillator.(cont.) These testing methods have been applied in the successful demonstration of a super-conducting bandpass AE modulator fabricated in a niobium integrated circuit process with 1 kA/cm2 critical current density for the Josephson junctions. At a 42.6 GHz sampling rate, the center frequency of the experimental modulator is 2.23 GHz, the measured SNR is 49 dB over a 20.8 MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2 GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6 MHz bandwidth.by John Francis Bulzacchelli.Ph.D

Precise Timing of Digital Signals: Circuits and Applications

With the rapid advances in process technologies, the performance of state-of-the-art integrated circuits is improving steadily. The drive for higher performance is accompanied with increased emphasis on meeting timing constraints not only at the design phase but during device operation as well. Fortunately, technology advancements allow for even more precise control of the timing of digital signals, an advantage which can be used to provide solutions that can address some of the emerging timing issues. In this thesis, circuit and architectural techniques for the precise timing of digital signals are explored. These techniques are demonstrated in applications addressing timing issues in modern digital systems. A methodology for slow-speed timing characterization of high-speed pipelined datapaths is proposed. The technique uses a clock-timing circuit to create shifted versions of a slow-speed clock. These clocks control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9ps in 0.18μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit itself. In order to achieve higher resolutions than that of an inverter/buffer stage, a differential (vernier) delay line is commonly used. To allow for the design of differential delay lines with programmable delays, a digitally-controlled delay-element is proposed. The delay element is monotonic and achieves a high degree of transfer characteristics' (digital code vs. delay) linearity. Using the proposed delay element, a sub-1ps resolution is demonstrated experimentally in 0.18μm CMOS. The proposed delay element with a fixed delay step of 2ps is used to design a high-precision all-digital phase aligner. High-precision phase alignment has many applications in modern digital systems such as high-speed memory controllers, clock-deskew buffers, and delay and phase-locked loops. The design is based on a differential delay line and a variation tolerant phase detector using redundancy. Experimental results show that the phase aligner's range is from -264ps to +247ps which corresponds to an average delay step of approximately 2.43ps. For various input phase difference values, test results show that the difference is reduced to less than 2ps at the output of the phase aligner. On-chip time measurement is another application that requires precise timing. It has applications in modern automatic test equipment and on-chip characterization of jitter and skew. In order to achieve small conversion time, a flash time-to-digital converter is proposed. Mismatch between the various delay comparators limits the time measurement precision. This is demonstrated through an experiment in which a 6-bit, 2.5ps resolution flash time-to-digital converter provides an effective resolution of only 4-bits. The converter achieves a maximum conversion rate of 1.25GSa/s

Design of High-Speed SerDes Transceiver for Chip-to-Chip Communications in CMOS Process

With the continuous increase of on-chip computation capacities and exponential growth of data-intensive applications, the high-speed data transmission through serial links has become the backbone for modern communication systems. To satisfy the massive data-exchanging requirement, the data rate of such serial links has been updated from several Gb/s to tens of Gb/s. Currently, the commercial standards such as Ethernet 400GbE, InfiniBand high data rate (HDR), and common electrical interface (CEI)-56G has been developing towards 40+ Gb/s. As the core component within these links, the transceiver chipset plays a fundamental role in balancing the operation speed, power consumption, area occupation, and operation range. Meanwhile, the CMOS process has become the dominant technology in modern transceiver chip fabrications due to its large-scale digital integration capability and aggressive pricing advantage. This research aims to explore advanced techniques that are capable of exploiting the maximum operation speed of the CMOS process, and hence provides potential solutions for 40+ Gb/s CMOS transceiver designs. The major contributions are summarized as follows. A low jitter ring-oscillator-based injection-locked clock multiplier (RILCM) with a hybrid frequency tracking loop that consists of a traditional phase-locked loop (PLL), a timing-adjusted loop, and a loop selection state-machine is implemented in 65-nm C-MOS process. In the ring voltage-controlled oscillator, a full-swing pseudo-differential delay cell is proposed to lower the device noise to phase noise conversion. To obtain high operation speed and high detection accuracy, a compact timing-adjusted phase detector tightly combined with a well-matched charge pump is designed. Meanwhile, a lock-loss detection and lock recovery is devised to endow the RILCM with a similar lock-acquisition ability as conventional PLL, thus excluding the initial frequency set- I up aid and preventing the potential lock-loss risk. The experimental results show that the figure-of-merit of the designed RILCM reaches -247.3 dB, which is better than previous RILCMs and even comparable to the large-area LC-ILCMs. The transmitter (TX) and receiver (RX) chips are separately designed and fab- ricated in 65-nm CMOS process. The transmitter chip employs a quarter-rate multi-multiplexer (MUX)-based 4-tap feed-forward equalizer (FFE) to pre-distort the output. To increase the maximum operating speed, a bandwidth-enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. The receiver chip employs a two-stage continuous-time linear equalizer (CTLE) as the analog front-end and integrates an improved clock data recovery to extract the sampling clocks and retime the incoming data. To automatically balance the jitter tracking and jitter suppression, passive low-pass filters with adaptively-adjusted bandwidth are introduced into the data-sampling path. To optimize the linearity of the phase interpolation, a time-averaging-based compensating phase interpolator is proposed. For equalization, a combined TX-FFE and RX-CTLE is applied to compensate for the channel loss, where a low-cost edge-data correlation-based sign zero-forcing adaptation algorithm is proposed to automatically adjust the TX-FFE’s tap weights. Measurement results show that the fabricated transmitter/receiver chipset can deliver 40 Gb/s random data at a bit error rate of 16 dB loss at the half-baud frequency, while consuming a total power of 370 mW

Design and distortion analysis of fully integrated image reject RF CMOS frontends

This thesis presents the design and experimental results of a 7.3GHz notch image reject filter, combined with a 5.8GHz low-noise amplifier (LNA), for integrated heterodyne receiver front-ends. A new image reject filter implementation is proposed. Q-enhancement circuitry for on-chip inductors are used to optimize the depth of image rejection. Experimental results show that more than 62dB of image rejection at 7.3GHz can be obtained in a standard CMOS 0.18mum technology, while operating from a 1.8V supply. The LNA exhibits a gain of 15.8dB and an IIP3 of -5.3dBm while consuming 9mW of power. With maximum image rejection, the LNA-notch combination circuit achieves a 4.1dB noise figure at 5.8GHz. The proposed notch filter alone can operate from a 1V supply voltage. It is shown analytically how circuit stability can be ensured.The implementation of new robust and stable high-Q CMOS image reject filters, which enables the realization of fully integrated heterodyne 5GHz RF receivers is also presented. A cascade of two notch filters with their image reject frequencies slightly offsetted is proposed, in order to obtain a wide image rejection bandwidth, without having to resort to the overhead of automatic tuning circuitry. Thus, power consumption, area, and complexity are significantly reduced. Experimental results show that more than 30d$ of image rejection can be obtained in a standard 0.18mum CMOS technology, over a 400MHz bandwidth centered at 7.4GHz