MICROSTRUCTURAL CHARACTERIZATION AND THERMAL CYCLING RELIABILITY OF SOLDERS UNDER ISOTHERMAL AGING AND ELECTRICAL CURRENT

Solder joints on printed circuit boards provide electrical and mechanical connections between electronic devices and metallized patterns on boards. These solder joints are often the cause of failure in electronic packages. Solders age under storage and operational life conditions, which can include temperature, mechanical loads, and electrical current. Aging occurring at a constant temperature is called isothermal aging. Isothermal aging leads to coarsening of the bulk microstructure and increased interfacial intermetallic compounds at the solder-pad interface. The coarsening of the solder bulk degrades the creep properties of solders, whereas the voiding and brittleness of interfacial intermetallic compounds leads to mechanical weakness of the solder joint. Industry guidelines on solder interconnect reliability test methods recommend preconditioning the solder assemblies by isothermal aging before conducting reliability tests. The guidelines assume that isothermal aging simulates a "reasonable use period," but do not relate the isothermal aging levels with specific use conditions. Studies on the effect of isothermal aging on the thermal cycling reliability of tin-lead and tin-silver-copper solders are limited in scope, and results have been contradictory. The effect of electrical current on solder joints has been has mostly focused on current densities above 104A/cm2 with high ambient temperature (≥100oC), where electromigration, thermomigration, and Joule heating are the dominant failure mechanisms. The effect of current density below 104A/cm2 on temperature cycling fatigue of solders has not been established. This research provides the relation between isothermal aging and the thermal cycling reliability of select Sn-based solders. The Sn-based solders with 3%, 1%, and 0% silver content that have replaced tin-lead are studied and compared against tin-lead solder. The activation energy and growth exponents of the Arrhenius model for the intermetallic growth in the solders are provided. An aging metric to quantify the aging of solder joints, in terms of phase size in the solder bulk and interfacial intermetallic compound thickness at the solder-pad interface, is established. Based on the findings of thermal cycling tests on aged solder assemblies, recommendations are made for isothermal aging of solders before thermal cycling tests. Additionally, the effect of active electrical current at 103 A/cm2 on thermal cycling reliability is reported

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection

Conventional tin-lead solder alloys have been widely used in electronics interconnection owing to their properties such as low melting temperature, good ductility and excellent wettability on copper and other substrates. However, due to the worldwide legislation addressing the concern over the toxicity of lead, the usage of lead-containing solders has been phased out, thus stimulating substantial efforts on lead-free alternatives, amongst which eutectic Sn-Ag and Sn-Cu, and particularly Sn-Ag-Cu alloys, are promising candidates as recommended by international parties. To meet the increasing demands of advanced electronic products, high levels of integration of electronic devices are being developed and employed, which is leading to a reduction in package size, but with more and more input/output connections. Flip chip technology is therefore seen as a promising technique for chip interconnection compared with wire bonding, enabling higher density, better heat dissipation and a smaller footprint. This thesis is intended to investigate lead-free (eutectic Sn-Ag, Sn-Cu and Sn-Ag-Cu) wafer level solder bumping through electrodeposition for flip chip interconnection, as well as electroplating lead-free solderable finishes on electronic components. The existing knowledge gap in the electrochemical processes as well as the fundamental understanding of the resultant tin-based lead-free alloys electrodeposits are also addressed. For the electrodeposition of the Sn-Cu solder alloys, a methanesulphonate based electrolyte was established, from which near-eutectic Sn-Cu alloys were achieved over a relatively wide process window of current density. The effects of methanesulphonic acid, thiourea and OPPE (iso-octyl phenoxy polyethoxy ethanol) as additives were investigated respectively by cathodic potentiodynamic polarisation curves, which illustrated the resultant electrochemical changes to the electrolyte. Phase identification by X-ray diffraction showed the electrodeposits had a biphasic structure (β-Sn and Cu6Sn5). Microstructures of the Sn-Cu electrodeposits were comprehensively characterised, which revealed a compact and crystalline surface morphology under the effects of additives, with cross-sectional observations showing a uniform distribution of Cu6Sn5 particles predominantly along β-Sn grain boundaries. The electrodeposition of Sn-Ag solder alloys was explored in another pyrophosphate based system, which was further extended to the application for Sn-Ag-Cu solder alloys. Cathodic potentiodynamic polarisation demonstrated the deposition of noble metals, Ag or Ag-Cu, commenced before the deposition potential of tin was reached. The co-deposition of Sn-Ag or Sn-Ag-Cu alloy was achieved with the noble metals electrodepositing at their limiting current densities. The synergetic effects of polyethylene glycol (PEG) 600 and formaldehyde, dependent on reaching the cathodic potential required, helped to achieve a bright surface, which consisted of fine tin grains (~200 nm) and uniformly distributed Ag3Sn particles for Sn-Ag alloys and Ag3Sn and Cu6Sn5 for Sn-Ag-Cu alloys, as characterised by microstructural observations. Near-eutectic Sn-Ag and Sn-Ag-Cu alloys were realised as confirmed by compositional analysis and thermal measurements. Near-eutectic lead-free solder bumps of 25 μm in diameter and 50 μm in pitch, consisting of Sn-Ag, Sn-Cu or Sn-Ag-Cu solder alloys depending on the process and electrolyte employed, were demonstrated on wafers through the electrolytic systems developed. Lead-free solder bumps were further characterised by material analytical techniques to justify the feasibility of the processes developed for lead-free wafer level solder bumping

Etude et caractérisation d'interconnexions intermétalliques à partir de plot de cuivre et d'alliage SnAgCu pour l'empilement tridimentionnel de composants actifs

Technological roadmap of the microelectronic industry is mainly described by Moore'slaw which aims a constant reduction of transistors size. Three-dimensional integration ofactive chips appears more and more as an alternative way to Moore's law. According to thisstrategy, chips are interconnected along the vertical axis thanks to copper pillars and a tinbased alloy (SnAgCu).The joining is then performed through eutectic bonding using aSnAgCu solder alloy which is at the origin of intermetallic compounds growing at the copperalloy interface. These intermetallic compounds are sometimes described in literature asweakening factor of the interconnection mechanical reliability. Moreover this interfacialreactivity leads also to the formation of Kirkendall microvoids potentially causinginterconnections breakings, mostly noticed during ageing tests.This report is dedicated to the study and metallurgical characterization of theinterconnection system with a size close to that of the actual prototypes which is 25μm. Thestudy is successively focused on SnAgCu alloy microstructure, Cu/SnAgCu and Ni/SnAgCuinterfacial reactivity and on the mechanical reliability of interconnection system. These topicsare investigated in function of thermal constraints and during different integration steps untilchips packaging. The main critical aspect is related to the fact that system dimensions, alreadysmall, are planned to be reduced, leading to a more important proportion of the solder alloyconsumed by interfacial reaction.Les objectifs technologiques de l'industrie de la microélectronique sont largement dictés par la loi de Moore qui vise une réduction permanente de la taille des transistors. Depuis peu l'intégration tridimensionnel de composant actif se présente comme une voie d'intégration alternative à la loi de Moore. Selon cette stratégie, les composants sont interconnectés selon l'axe verticale au moyen de plots de cuivre et d'un alliage à base d'étain (SnAgCu). L'assemblage est alors réalisé par un brasage eutectique de l'alliage SnAgCu qui génère une formation de composés intermétalliques (Cu6Sn6 et Cu3Sn) à l'interface entre les plots de cuivre et l'alliage. Or, ces composés intermétalliques sont parfois décrits dans la littérature comme facteur affaiblissant la fiabilité mécanique de l'interconnexion. Par ailleurs cette réactivité interfaciale s'accompagne de l'apparition microcavités de type trous Kirkendall susceptibles d'être à l'origine de ruptures d'interconnexions notée lors de tests de vieillissement. Ce mémoire est consacré à la caractérisation métallurgique du système d'interconnexion par brasage dont les dimensions sont celles des prototypes actuels c'est-à-dire 25µm. L'étude se concentrera successivement sur les aspects relatifs à la microstructure de l'alliage SnAgCu, à la réactivité interfaciale des systèmes Cu/SnAgCu et Ni/SnAgCu puis à la fiabilité mécanique du système d'interconnexion. Ces thématiques seront investiguées en fonction de la contrainte thermique et au cours des différentes étapes d'intégration jusqu'à l'assemblage de composant. Le caractère critique de la problématique réside dans le fait que les dimensions du système, déjà faibles, ont vocation à se réduire, rendant de plus en plus importante la proportion du volume de l'alliage occupée par ces formations interfaciales

Semiconductor Packaging

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages

Semiconductor Packaging

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures