Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models

Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. Any device that can reduce the load on, for example, a PC’s processor, is advantageous. Hence we present FPGA implementations of the decoder based alternately on discrete and continuous hidden Markov models (HMMs) representing monophones, and demonstrate that the discrete version can process speech nearly 5,000 times real time, using just 12% of the slices of a Xilinx Virtex XCV1000, but with a lower recognition rate than the continuous implementation, which is 75 times faster than real time, and occupies 45% of the same device

Efficient Embedded Speech Recognition for Very Large Vocabulary Mandarin Car-Navigation Systems

Automatic speech recognition (ASR) for a very large vocabulary of isolated words is a difficult task on a resource-limited embedded device. This paper presents a novel fast decoding algorithm for a Mandarin speech recognition system which can simultaneously process hundreds of thousands of items and maintain high recognition accuracy. The proposed algorithm constructs a semi-tree search network based on Mandarin pronunciation rules, to avoid duplicate syllable matching and save redundant memory. Based on a two-stage fixed-width beam-search baseline system, the algorithm employs a variable beam-width pruning strategy and a frame-synchronous word-level pruning strategy to significantly reduce recognition time. This algorithm is aimed at an in-car navigation system in China and simulated on a standard PC workstation. The experimental results show that the proposed method reduces recognition time by nearly 6-fold and memory size nearly 2- fold compared to the baseline system, and causes less than 1% accuracy degradation for a 200,000 word recognition task

Comparative Study of Various Systems on Chips Embedded in Mobile Devices

Systems-on-chips (SoCs) are the latest incarnation of very large scale integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors. Harnessing all this computing power requires designers to move beyond logic design into computer architecture, meet real-time deadlines, ensure low-power operation, and so on. These opportunities and challenges make SoC design an important field of research. So in the paper we will try to focus on the various aspects of SOC and the applications offered by it. Also the different parameters to be checked for functional verification like integration and complexity are described in brief. We will focus mainly on the applications of system on chip in mobile devices and then we will compare various mobile vendors in terms of different parameters like cost, memory, features, weight, and battery life, audio and video applications. A brief discussion on the upcoming technologies in SoC used in smart phones as announced by Intel, Microsoft, Texas etc. is also taken up. Keywords: System on Chip, Core Frame Architecture, Arm Processors, Smartphone

Development of PCI Embedded Card Useful for Microcontroller Trainer

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Bluetooth Based Data Acquisition System

Data acquisition systems are devices used to collect information to document or analyze some physical phenomenon such as voltage, force or temperature. Data acquisition systems available in the market are very expensive, bulky and power hungry. However, PC based data acquisition system offers a lot of benefit in terms of processing speed, display resolution and connectivity capabilities. The Project aims at designing and implementing a portable, economical and power efficient real-time data acquisition system. The proposed system comprises of a hardware circuitry and a Graphical User Interface (GUI) based on MATLAB environment. The hardware device consist of an 8-bit microcontroller interfaced with a serial ADC chip and a Bluetooth serial module. The Bluetooth HC-05 module is used to provide a wireless connectivity between the hardware and the PC. For testing purpose, the sampling rate of ADC is set to 833 Hz, capturing 50 values per 0.06 second. Whereas on the PC side, the GUI receives the sampled values transmitted by the hardware device and plots the real-time signal waveform. It has been found that the GUI plots the signal waveform with good quality and efficiency. The proposed system can be deployed in number of industrial application such as remote device controlling and ECG data acquisition with some adjustments in the hardware. The wireless connectivity reduces the complexity of cables and probability of occurrences of the accidents in industrial areas