Flexible Smart Display with Integrated Graphics Rasterizor using Single Grain TFTs

Flexible electronics is a fast emerging market and includes electronics fabricated on flexible substrates, large area displays, low cost and  disposable electronics. Both research and commercial institutions around the world have been trying to develop low temperature processes which will enable fabrication of electronic devices on arbitrary substrates including glass and plastic. While most of these technologies are still in the research phase, many approaches have shown promising results. One such  technology is being developed in DIMES, TU Delft which uses single grain silicon crystals to fabricate Single Grain Thin Film Transistors (SG-TFTs) at plastic compatible temperatures. SG-TFTs and other similar technologies can potentially enable fabricating electronics directly on arbitrary  substrates. This would further enable integration of embedded intelligence in devices that would enhance the current functionalists of displays. This paper is an effort in this direction as it undertakes a study to design a  flexible display with an integrated graphics rasterizor unit. The paper  introduces the novel idea to move parts of the graphics pipeline from the CPU/GPU to the display. This will add intelligence to the display so as to realize a smart-display. The paper proposes several architectures for  implementing a rasterizor unit on smart-display, conceptually fabricated on a flexible substrate using SG-TFT technology. While the transistors  fabricated with SG-TFT and similar technologies are relatively slower than the standard CMOS, this paper proposes and concludes that a tile based system design can potentially result into enhanced system performance

Excimer Laser Crystallization of Silicon Thin-Films for Monolithic 3D Integration

In 1964 the first metal oxide semiconductor (MOS) integrated circuit (IC) became available. Shortly after in 1965 Gordon Moore predicted the pace of the device density increase in ICs. His prediction became a self-fulfilling prophecy, which taking advantage of the formal device scaling rules introduced by Robert Dennard in 1974, drove the evolution of the integrated electronic industry. In conventional two dimensional ICs, devices are integrated into a single layer of silicon in what is called the front end of line (FEOL) fabrication. Additional layers on top of the devices serve as inter-dielectric isolating layer and metal interconnects and are fabricated in the back end of line (BEOL) process. Scaling the dimension of devices allows for an increase in device density, improvement on device switching speed and reduction of the cost per device. The conjunction of these benefits drove the industry thus far. Over the past decade further scaling the devices while achieving also an increase in performance and cost benefits became extremely difficult. As the dimensional scaling of complementary MOS (CMOS) devices reaches its limits, three dimensional ICs (3DICs) are increasingly being considered as a path to achieve higher device densities. 3DICs offer a way to increase density by using multiple device layers on the same die, reducing the interconnect distance and allowing for a decrease in signal delay. Among different fabrication techniques, monolithic 3D integration is potentially more cost effective but requires high performance devices, a process compatible with transistor integration in the BEOL stack and needs to deliver a high device density and uniformity in order to be adopted by the very large scale integration (VLSI) industry. This work focuses on a particular laser crystallization technique to achieve monolithic device integration. The technique, called Excimer Laser Crystallization (ELC), makes use of an excimer laser to achieve a large grain polycrystalline thin-film starting from an amorphous layer, allowing integration of high quality thin-film transistors (TFTs). Thus far, the ELC technique has been studied on thin-films typically deposited on top of quartz substrate or Si/SiO₂ wafers. On the other hand state of the art VLSI integration uses more advance BEOL stacks with low-κ material as interlayer dielectrics (ILDs) to passivate the copper (Cu) interconnect lines. This thesis focuses on three different key aspect to enable laser crystallization in the BEOL for device integration: 1. Excimer laser crystallization of amorphous silicon on low-κ dielectric; 2. Excimer laser crystallization of amorphous silicon on BEOL processed wafer; 3. VLSI of TFTs on excimer laser crystallized silicon. The ELC of amorphous silicon on low-κ dielectric is first explored through one dimension (1D) finite element method (FEM) simulation of the temperature evolution during the laser exposure in two different systems: 1. amorphous silicon deposited on top of SiO₂ dielectric; 2. amorphous silicon deposited on top of low-κ dielectric. Simulations predict that is necessary a lower laser energy for crystallizing the silicon on the low-κ material. Experimental observations confirm the predicted behavior yielding a 35% lower energy for crystallization of thin-film silicon on top of a low-κ dielectric. Material characterization through defect enhanced SEM micrograph, Raman spectroscopy and XRD analysis shows an equivalent material morphology for the two system with a preferential (111) crystal orientation for the SiO₂ system. Silicon crystallization on BEOL processed wafer is studied through a combination of 1D FEM simulation and experimental observation on a silicon layer deposited on top of a SiO₂dielectric protecting the underlying damascene Cu structure. 1D FEM show that during the silicon laser exposure, because of the short pulse width of the laser (30 ns), the heat is retained in the amorphous silicon layer allowing its melting while keeping the temperature of the Cu lines below 320 °C which is a favorable condition for monolithic integration in the BEOL. Further experimental evidences show the ability of crystallizing a-Si on such structure while preserving the physical and electrical properties of the Cu lines. The feasibility of monolithic VLSI 3D integration is demonstrated through integration of TFTs devices on 200 mm silicon wafers. The integration process and performance of the TFTs device are modeled through technology computer aided design (TCAD) simulations which are used to define the process flow and the fabrication parameters. Characterization of the TFTs over multiple die yield good device performance and uniformity. TFTs characterized with 1.5 V of supply voltage have a sub-threshold slope down to 79 mV/decade, current density up to 26.3 μA/μm, a threshold voltage of 0.23 V, current On/Off ratio above 10⁵ and device field effect mobility up to 19.8 cm²/(V s) for LPCVD-sourced silicon. Furthermore, the Levinson method allows characterization of the trap density in the thin-film polysilicon devices yielding a mean value 8.13×10¹² cm². This work present an integration scheme which proves to be compatible with VLSI in the BEOL of wafers. It paves the way to further development which could lead to an high performance, cost effective, monolithic 3D integration approach useful in application such as reconfigurable logic, display, heterogeneous integration and on chip optical communications

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Layer by layer printing of nanomaterials for large-area, flexible electronics

Large-area electronics, including printable and flexible electronics, is an emerging concept which aims to develop electronic components in a cheaper and faster manner, especially on those non-conventional substrates. Being flexible and deformable, this new form of electronics is regarded to hold great promises for various futuristic applications including the internet of things, virtual reality, healthcare monitoring, prosthetics and robotics. However, at present, large-area electronics is still nowhere near the commercialisation stage, which is due to several problems associated with performance, uniformity and reliability, etc. Moreover, although the device’s density is not the major concern in printed electronics, there is still a merit in further increasing the total number of devices in a limited area, in order to achieve more electronic blocks, higher performance and multiple functionalities. In this context, this Ph.D. thesis focuses on the printing of various nanomaterials for the realisation of high-performance, flexible and large-area electronics. Several aspects have been covered in this thesis, including the printing dynamics of quasi-1D NWs, the contact problem in device realisation and the strategy to achieve sequential integration (3D integration) of the as-printed devices, both on rigid and flexible substrates. Promisingly, some of the devices based on the printed nanomaterial show a comparable performance to the state-of-the-art technology. With the demonstrated 3D integration strategy, a highly dense array of electronic devices can be potentially achieved by printing method. This thesis also touches on the problem associated with the circuit and system realisation. Specifically, graphene-based logic gates and NW based UV sensing circuit has been discussed, which shows the promising applications of nanomaterial-based electronics. Future work will be focusing on extending the UV sensing circuit to an active matrix sensor array

Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems

A walk on the frontier of energy electronics with power ultra-wide bandgap oxides and ultra-thin neuromorphic 2D materials

Altres ajuts: the ICN2 is funded also by the CERCA programme / Generalitat de CatalunyaUltra-wide bandgap (UWBG) semiconductors and ultra-thin two-dimensional materials (2D) are at the very frontier of the electronics for energy management or energy electronics. A new generation of UWBG semiconductors will open new territories for higher power rated power electronics and deeper ultraviolet optoelectronics. Gallium oxide - GaO(4.5-4.9 eV), has recently emerged as a suitable platform for extending the limits which are set by conventional (-3 eV) WBG e.g. SiC and GaN and transparent conductive oxides (TCO) e.g. In2O3, ZnO, SnO2. Besides, GaO, the first efficient oxide semiconductor for energy electronics, is opening the door to many more semiconductor oxides (indeed, the largest family of UWBGs) to be investigated. Among these new power electronic materials, ZnGa2O4 (-5 eV) enables bipolar energy electronics, based on a spinel chemistry, for the first time. In the lower power rating end, power consumption also is also a main issue for modern computers and supercomputers. With the predicted end of the Moores law, the memory wall and the heat wall, new electronics materials and new computing paradigms are required to balance the big data (information) and energy requirements, just as the human brain does. Atomically thin 2D-materials, and the rich associated material systems (e.g. graphene (metal), MoS2 (semiconductor) and h-BN (insulator)), have also attracted a lot of attention recently for beyond-silicon neuromorphic computing with record ultra-low power consumption. Thus, energy nanoelectronics based on UWBG and 2D materials are simultaneously extending the current frontiers of electronics and addressing the issue of electricity consumption, a central theme in the actions against climate chang

Advances in Amorphous Oxide Semiconductor Devices, Materials, and Processes for Customizable Scalable Manufacturing of Thin-Film Electronics

Electronic circuits comprised of thin-film transistors (TFTs) are essential to nearly every modern display technology. For decades, the TFT industry relied on amorphous silicon, but increasing performance demands required semiconductors with superior electron transport leading to the adoption of amorphous oxide semiconductors (AOS). The superior electron transport and ease of thin-film preparation of AOS has led to a growing interest in developing thin-film electronics for beyond-display technologies. These include monolithic 3D integration on Si complementary metal-oxide-semiconductor integrated circuits (ICs) – to continue Moore’s law, add new functionality, and improve performance – and flexible electronics for electronic skins, textiles, solar cells, and displays. In this thesis we facilitate the adoption of thin-film electronics for beyond-display technologies by: 1) developing uniform and conformal AOS deposition processes with record performance; 2) demonstrating expanded AOS capabilities by exploring new device architectures; and 3) developing a new additive manufacturing technique for customizable scalable manufacturing. First, we meet the performance and thermal budget requirements of AOS for beyond-display applications by using atomic-layer deposition (ALD) – a conformal, uniform, and precise vapor-phase deposition technique – and aggressively optimizing the process conditions. We discovered that improved electrical performance correlated with an increase in film density, which can be achieved by increasing deposition temperature, by post-deposition annealing, and by using plasma enhanced-ALD (PE-ALD). Second, we made innovations in device design to expand the range of circuit applications for AOS TFTs by exploiting the benefit of their wide-bandgap to fabricate high-voltage TFTs (HVTFTs). While the current handling capabilities of these HVTFTs cannot compete with conventional power electronics, the ability to deposit AOS materials directly on Si ICs may enable monolithic 3D integration of HVTFTs, adding new functionality as an HV interface to aggressively scaled low-voltage Si CMOS. Third, we show that ambient instabilities are caused by interactions between the surface of the AOS film and ambient molecules. We eliminate these instabilities by developing an ALD-based passivation layer. Fourth, we study the temporal and bias stress stability of our ALD AOS thin-film transistors and see excellent stability after the first month of aging and improved positive bias stress stability with passivation. Fifth, we investigate several materials to form a Schottky contact to ALD AOS films to enable future rectifier-based circuits and unipolar logic circuits. Finally, we develop an additive manufacturing approach for customizable manufacturing of AOS devices. Further improvement in device performance and reduction of channel length, enabled by the sub-µm precision of EHD, has the potential to yield fully customizable additive manufacturing of high-frequency circuits.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169721/1/allemang_1.pd

Large-Scale Graphene Film Deposition for Monolithic Device Fabrication

Since 1958, the concept of integrated circuit (IC) has achieved great technological developments and helped in shrinking electronic devices. Nowadays, an IC consists of more than a million of compacted transistors. The majority of current ICs use silicon as a semiconductor material. According to Moore\u27s law, the number of transistors built-in on a microchip can be double every two years. However, silicon device manufacturing reaches its physical limits. To explain, there is a new trend to shrinking circuitry to seven nanometers where a lot of unknown quantum effects such as tunneling effect can not be controlled. Hence, there is an urgent need for a new platform material to replace Si. Graphene is considered a promising material with enormous potential applications in many electronic and optoelectronics devices due to its superior properties. There are several techniques to produce graphene films. Among these techniques, chemical vapor deposition (CVD) offers a very convenient method to fabricate films for large-scale graphene films. Though CVD method is suitable for large area growth of graphene, the need for transferring a graphene film to silicon-based substrates is required. Furthermore, the graphene films thus achieved are, in fact, not single crystalline. Also, graphene fabrication utilizing Cu and Ni at high growth temperature contaminates the substrate that holds Si CMOS circuitry and CVD chamber as well. So, lowering the deposition temperature is another technological milestone for the successful adoption of graphene in integrated circuits fabrication. In this research, direct large-scale graphene film fabrication on silicon based platform (i.e. SiO2 and Si3N4) at low temperature was achieved. With a focus on low-temperature graphene growth, hot-filament chemical vapor deposition (HF-CVD) was utilized to synthesize graphene film using 200 nm thick nickel film. Raman spectroscopy was utilized to examine graphene formation on the bottom side of the Ni film and on the silicon-based substrate. Large- area bilayer graphene film was formed on silicon based platform. COMSOL Multiphysics was used to investigate the CVD graphene growth on Ni films. Factors affecting CVD graphene synthesis include carbon solubility in Ni, growth time, growth temperature, as well as Ni film thickness. COMSOL model uses transport of diluted species, heat transfer in Ni thin film as well as deformed geometry module. In this particular research, the number of simulated graphene layers on Ni film was compared with experimental data. Also, the effect of many CVD parameters on graphene film fabrication is stated. In conclusion, a novel method for direct large-scale graphene film fabrication on silicon based platform at low temperature was achieved using hot-filament chemical vapor deposition

Solution-processed Amorphous Oxide Semiconductors for Thin-film Power Management Circuitry

Thin-film electronics has opened up new applications not achievable by wafer-based electronics. Following commercial success in displays and solar cells, the future industry sectors for thin film devices are limitless, and include novel wearable electronics and medical devices. Such new applications enabled by human-size electronics have been widely investigated, but their potential use in power-management circuitry has been seldom addressed. The key strengths of thin-film electronics are that they can be deposited on various substrates at a large-area scale, and they can be additively deposited on existing device layers without degrading them. These advantageous features can be used to overcome the current barriers facing silicon (Si) electronics in power-management applications. Namely, thin film electronics can be used to directly deposit circuits including power harvesters on RFID tags to reduce the current tag cost based on Si IC. Furthermore, they can be directly heterointegrated with Si chips to enhance their voltage handling capability. Finally, thin film electronics can be deposited onto solar cell arrays to improve efficiency by managing partial shading conditions. Among thin-film materials, we explore the scope of solution-derived amorphous oxide semiconductor (AOS) due to its high carrier mobility, wide band-gap, and in-air deposition capability. In this thesis, we push the boundaries of AOS by (i) developing an air-stable, ink-based deposition process for high-performance amorphous zinc-tin-oxide semiconductor. We choose a deposition process based on metal-organic decomposition, such that the film properties are independent of relative humidity in the deposition ambient, enabling future large-area roll-to-roll processing. (ii) Second, by exploiting in situ chemical evolution, namely reduction and oxidation, at the interface of zinc-tin-oxide and various metal electrodes (primarily Pd, Mo, and Ag), we intentionally manipulate the electrode contact properties to form high-quality ohmic contacts and Schottky barriers. We explain the results based on competing thermodynamic processes and interlayer diffusion. (iii) Third, we combine these techniques to fabricate novel devices, namely vertically-conducting thin-film diodes and Schottky-gated TFTs, and we investigate the impact of the contact formation process on the resulting device physics using temperature-dependent current-voltage measurements. (iv) Finally, we demonstrate the use of these devices in several novel thin-film power electronics applications. These circuits include thin-film RFID energy harvesters, thin-film heterointegrated 3D-IC on Si chip for voltage bridging, and thin-film bypass diodes for future integration on solar cells to improve efficiency under partial shading conditions.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/149911/1/ybson_1.pd

2D Materials Graphene related materials for thermal management Graphene related materials for thermal management

International audienceAlmost 15 years have gone ever since the discovery of graphene as a single atom layer. Numerous papers have been published to demonstrate its high electron mobility, excellent thermal and mechanical as well as optical properties. We have recently seen more and more applications towards using graphene in commercial products. This paper is an attempt to review and summarize the current status of the research of the thermal properties of graphene and other 2D based materials including the manufacturing and characterization techniques and their applications, especially in electronics and power modules. It is obvious from the review that graphene has penetrated the market and gets more and more applications in commercial electronics thermal management context. In the paper, we also made a critical analysis of how mature the manufacturing processes are; what are the accuracies and challenges with the various characterization techniques and what are the remaining questions and issues left before we see further more applications in this exciting and fascinating field. TOPICAL REVIE