KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs

In a modern FPGA system-on-chip design, it is often insufficient to simply assess the total power consumption of the entire circuit by design-time estimation or runtime power rail measurement. Instead, to make better runtime decisions, it is desirable to understand the power consumed by each individual module in the system. In this work, we combine boardlevel power measurements with register-level activity counting to build an online model that produces a breakdown of power consumption within the design. Online model refinement avoids the need for a time-consuming characterisation stage and also allows the model to track long-term changes to operating conditions. Our flow is named KAPow, a (loose) acronym for ‘K’ounting Activity for Power estimation, which we show to be accurate, with per-module power estimates as close to ±5mW of true measurements, and to have low overheads. We also demonstrate an application example in which a permodule power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by over 8%

Tau and atrophy: domain-specific relationships with cognition.

BackgroundLate-onset Alzheimer's disease (AD) is characterized by primary memory impairment, which then progresses towards severe deficits across cognitive domains. Here, we report how performance in cognitive domains relates to patterns of tau deposition and cortical thickness.MethodsWe analyzed data from 131 amyloid-β positive participants (55 cognitively normal, 46 mild cognitive impairment, 30 AD) of the Alzheimer's Disease Neuroimaging Initiative who underwent magnetic resonance imaging (MRI), flortaucipir (FTP) positron emission tomography, and neuropsychological testing. Surface-based vertex-wise and region-of-interest analyses were conducted between FTP and cognitive test scores, and between cortical thickness and cognitive test scores.ResultsFTP and thickness were differentially related to cognitive performance in several domains. FTP-cognition associations were more widespread than thickness-cognition associations. Further, FTP-cognition patterns reflected cortical systems that underlie different aspects of cognition.ConclusionsOur findings indicate that AD-related decline in domain-specific cognitive performance reflects underlying progression of tau and atrophy into associated brain circuits. They also suggest that tau-PET may have better sensitivity to this decline than MRI-derived measures of cortical thickness

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

MIDAS, prototype Multivariate Interactive Digital Analysis System for large area earth resources surveys. Volume 1: System description

A third-generation, fast, low cost, multispectral recognition system (MIDAS) able to keep pace with the large quantity and high rates of data acquisition from large regions with present and projected sensots is described. The program can process a complete ERTS frame in forty seconds and provide a color map of sixteen constituent categories in a few minutes. A principle objective of the MIDAS program is to provide a system well interfaced with the human operator and thus to obtain large overall reductions in turn-around time and significant gains in throughput. The hardware and software generated in the overall program is described. The system contains a midi-computer to control the various high speed processing elements in the data path, a preprocessor to condition data, and a classifier which implements an all digital prototype multivariate Gaussian maximum likelihood or a Bayesian decision algorithm. Sufficient software was developed to perform signature extraction, control the preprocessor, compute classifier coefficients, control the classifier operation, operate the color display and printer, and diagnose operation

Bridging the Testing Speed Gap: Design for Delay Testability

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addresse