Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost pro le. Thus, this D-latch may be useful for high reliability and high-performance safety-critical applications as it can detect and recover faults happening during holding time in harsh radiation environments. The proposed D-latch design is based on a low-cost single event double-node upset tolerant latch and a rule-based double-node upset (DNU) tolerant latch which provides it with the self-recoverability against DNU, but paired with a low transistor count and high performance. Simulation waveforms support the achievements and demonstrate that this new D-latch is fully self-recoverable against double-node upset. In addition, the minimum improvement of the delay-power-area product of the proposed rule-based design for the low-cost DNU tolerant self-recoverable latch (RB-LDNUR) is 59%, compared with the latest DNU self-recoverable latch on the literature.Spanish Government MCIN/AEI/10.13039/501100011033/FEDER PID2020-117344RB-I00Regional Government P20_00265 P20_00633 B-RNM-680-UGR2

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

This work was supported in part by the Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00, and in part by the Regional Government under Grant P20_00265 and Grant P20_00633.As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU) tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features; in particular, this approach enhances its reliability against process variations, such as threshold voltage and (W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch: it can mask single event transients. Speci c gures of merit endorse the gains introduced by the new design: compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8% and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch.Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00Regional Government under Grant P20_00265 and Grant P20_0063

Investigation of radiation-hardened design of electronic systems with applications to post-accident monitoring for nuclear power plants

This research aims at improving the robustness of electronic systems used-in high level radiation environments by combining with radiation-hardened (rad-hardened) design and fault-tolerant techniques based on commercial off-the-shelf (COTS) components. A specific of the research is to use such systems for wireless post-accident monitoring in nuclear power plants (NPPs). More specifically, the following methods and systems are developed and investigated to accomplish expected research objectives: analysis of radiation responses, design of a radiation-tolerant system, implementation of a wireless post-accident monitoring system for NPPs, performance evaluation without repeat physical tests, and experimental validation in a radiation environment. A method is developed to analyze ionizing radiation responses of COTS-based devices and circuits in various radiation conditions, which can be applied to design circuits robust to ionizing radiation effects without repeated destructive tests in a physical radiation environment. Some mathematical models of semiconductor devices for post-irradiation conditions are investigated, and their radiation responses are analyzed using Technology Computer Aided Design (TCAD) simulator. Those models are then used in the analysis of circuits and systems under radiation condition. Based on the simulation results, method of rapid power off may be effectively to protect electronic systems under ionizing radiation. It can be a potential solution to mitigate damages of electronic components caused by radiation. With simulation studies of photocurrent responses of semiconductor devices, two methods are presented to mitigate the damages of total ionizing dose: component selection and radiation shielding protection. According to the investigation of radiation-tolerance of regular COTS components, most COTS-based semiconductor components may experience performance degradation and radiation damages when the total dose is greater than 20 K Rad (Si). A principle of component selection is given to obtain the suitable components, as well as a method is proposed to assess the component reliability under radiation environments, which uses radiation degradation factors, instead of the usual failure rate data in the reliability model. Radiation degradation factor is as the input to describe the radiation response of a component under a total radiation dose. In addition, a number of typical semiconductor components are also selected as the candidate components for the application of wireless monitoring in nuclear power plants. On the other hand, a multi-layer shielding protection is used to reduce the total dose to be less than 20 K Rad (Si) for a given radiation condition; the selected semiconductor devices can then survive in the radiation condition with the reduced total dose. The calculation method of required shielding thickness is also proposed to achieve the design objectives. Several shielding solutions are also developed and compared for applications in wireless monitoring system in nuclear power plants. A radiation-tolerant architecture is proposed to allow COTS-based electronic systems to be used in high-level radiation environments without using rad-hardened components. Regular COTS components are used with some fault-tolerant techniques to mitigate damages of the system through redundancy, online fault detection, real-time preventive remedial actions, and rapid power off. The functions of measurement, processing, communication, and fault-tolerance are integrated locally within all channels without additional detection units. A hardware emulation bench with redundant channels is constructed to verify the effectiveness of the developed radiation-tolerant architecture. Experimental results have shown that the developed architecture works effectively and redundant channels can switch smoothly in 500 milliseconds or less when a single fault or multiple faults occur. An online mechanism is also investigated to timely detect and diagnose radiation damages in the developed redundant architecture for its radiation tolerance enhancement. This is implemented by the built-in-test technique. A number of tests by using fault injection techniques have been carried out in the developed hardware emulation bench to validate the proposed detection mechanism. The test results have shown that faults and errors can be effectively detected and diagnosed. For the developed redundant wireless devices under given radiation dose (20 K Rad (Si)), the fault detection coverage is about 62.11%. This level of protection could be improved further by putting more resources (CPU consumption, etc.) into the function of fault detection, but the cost will increase. To apply the above investigated techniques and systems, under a severe accident condition in a nuclear power plant, a prototype of wireless post-accident monitoring system (WPAMS) is designed and constructed. Specifically, the radiation-tolerant wireless device is implemented with redundant and diversified channels. The developed system operates effectively to measure up-to-date information from a specific area/process and to transmit that information to remote monitoring station wirelessly. Hence, the correctness of the proposed architecture and approaches in this research has been successfully validated. In the design phase, an assessment method without performing repeated destructive physical tests is investigated to evaluate the radiation-tolerance of electronic systems by combining the evaluation of radiation protection and the analysis of the system reliability under the given radiation conditions. The results of the assessment studies have shown that, under given radiation conditions, the reliability of the developed radiation-tolerant wireless system can be much higher than those of non-redundant channels; and it can work in high-level radiation environments with total dose up to 1 M Rad (Si). Finally, a number of total dose tests are performed to investigate radiation effects induced by gamma radiation on distinct modern wireless monitoring devices. An experimental setup is developed to monitor the performance of signal measurement online and transmission of the developed distinct wireless electronic devices directly under gamma radiator at The Ohio State University Nuclear Reactor Lab (OSU-NRL). The gamma irradiator generates dose rates of 20 K Rad/h and 200 Rad/h on the samples, respectively. It was found that both measurement and transmission functions of distinct wireless measurement and transmission devices work well under gamma radiation conditions before the devices permanently damage. The experimental results have also shown that the developed radiation-tolerant design can be applied to effectively extend the lifespan of COTS-based electronic systems in the high-level radiation environment, as well as to improve the performance of wireless communication systems. According to testing results, the developed radiation-tolerant wireless device with a shielding protection can work at least 21 hours under the highest dose rate (20 K Rad/h). In summary, this research has addressed important issues on the design of radiation-tolerant systems without using rad-hardened electronic components. The proposed methods and systems provide an effective and economical solution to implement monitoring systems for obtaining up-to-date information in high-level radiation environments. The reported contributions are of significance both academically and in practice