Spanning Tree Transformation of Connected Graph into Single-Row Network

A spanning tree of a connected graph is a tree which consists the set of vertices and some or perhaps all of the edges from the connected graph. In this paper, a model for spanning tree transformation of connected graphs into single-row networks, namely Spanning Tree of Connected Graph Modeling (STCGM) will be introduced. Path-Growing Tree-Forming algorithm applied with Vertex-Prioritized is contained in the model to produce the spanning tree from the connected graph. Paths are produced by Path-Growing and they are combined into a spanning tree by Tree-Forming. The spanning tree that is produced from the connected graph is then transformed into single-row network using Tree Sequence Modeling (TSM). Finally, the single-row routing problem is solved using a method called Enhanced Simulated Annealing for Single-Row Routing (ESSR)

SINGLE-ROW ROUTING PROBLEM WITH ALTERNATIVE TERMINALS

The present article concentrates on the dogleg-free Manhattan model where horizontal and vertical wire segments are positioned on different sides of the board and each net (wire) has at most one horizontal segment. Gallai's classical result on interval packing can be applied in VLS1 routing to find, in linear time, a minimum-width dogleg-free routing in the Manhattan model, provided that all the terminals are on one side of a rectangular (single-row routing). We deal with the generalization of this routing problem when we have the possibility to select another terminal from a corresponding set instead of a terminal to be connected. It will be shown that in this case there is no hope to find a polynomial algorithm because this problem is NP-complete. The results on dogleg-free Manhattan routing can be connected with other application areas related to colouring of interval graphs. In this paper the alternative interval placement problem will be defined. We show that this problem is NP-complete. This implies the NP-completeness of the single-row routing problem with alternative terminals

ROUTING WITH MINIMUM WIRE LENGTH IN THE MANHATTAN MODEL IS NP-COMPLETE

The present paper concentrates on one of the most common routing models, on the Manhattan model where horizontal and vertical wire segments are positioned on different sides of the board. While the minimum width can be found in linear time in the single row routing, apparently there was no efficient algorithm to find the minimum wire length. We showed before that this problem is NP-complete in the dogleg-free case but the complexity of the problem was still unknown in the general case. In this paper we modify the construction applied in the former proof in order to show the NP-completeness of routing with minimum wire length in the Manhattan model without any restrictions

The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms

With the advent of VLSI technology, circuits with more than one million transistors have been integrated onto a single chip. As the complexity of ICs grows, the time and money spent on designing the circuits become more important. A large, often dominant, part of the cost and time required to design an IC is consumed in the routing operation. The routing of carriers, such as in IC chips and printed circuit boards, is a classical problem in Computer Aided Design. With the complexity inherent in VLSI circuits, high performance routers are necessary. In this paper, a crucial step in the channel routing technique, the single row routing (SRR) problem, is considered. First, we discuss the relevance of SRR in the context of the general routing problem. Secondly, we show that heuristic algorithms are far from solving the general problem. Next, we introduce evolutionary computation, and, in particular, genetic algorithms (GAs) as a justifiable method in solving the SRR problem. Finally, an efficient O(nk) complexity technique based on GAs heuristic is obtained to solve the general SRR problem containing n nodes. Experimental results show that the algorithm is faster and can often generate better results than many of the leading heuristics proposed in the literature

Deterministic 1-k routing on meshes with applications to worm-hole routing

In $1$-$k$ routing each of the $n^2$ processing units of an $n \times n$ mesh connected computer initially holds $1$ packet which must be routed such that any processor is the destination of at most $k$ packets. This problem reflects practical desire for routing better than the popular routing of permutations. $1$-$k$ routing also has implications for hot-potato worm-hole routing, which is of great importance for real world systems. We present a near-optimal deterministic algorithm running in \sqrt{k} \cdot n / 2 + \go{n} steps. We give a second algorithm with slightly worse routing time but working queue size three. Applying this algorithm considerably reduces the routing time of hot-potato worm-hole routing. Non-trivial extensions are given to the general $l$-$k$ routing problem and for routing on higher dimensional meshes. Finally we show that $k$-$k$ routing can be performed in \go{k \cdot n} steps with working queue size four. Hereby the hot-potato worm-hole routing problem can be solved in \go{k^{3/2} \cdot n} steps

dRail: a novel physical layout methodology for power gated circuits

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layou

OPTIMAL ROUTING ON NARROW CHANNELS

Channel routing is one of the basic problems in VLSI routing. While the minimum width can be found in linear time in the single row routing problem, the complexity of the channel routing problem is not fully understood yet. A solution can be found, even in linear time, in the unconstrained model, but the complexity of determining the minimum width is not known. The present article concentrates on the Manhattan model where horizontal and vertical wire segments are positioned on different sides of the board. In this case, the routing problem is known to be NP-complete. Hence there is no hope to find an algorithm whose running time is polynomial both in the length and the width of the channel. The width of the channel is usually much smaller than the length, thus, an algorithm, whose running time is exponential in the width and polynomial' in the length can be efficient in the case of a narrow channel. We show that the channel routing problem in the Manhattan model is solvable in linear time if the length of the input is proportional to the length of the channel, and the width does not belong to the input