Layout optimization in ultra deep submicron VLSI design

As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a linear-time tree partitioning algorithm. At the track assignment stage, timing is further optimized using a graph based technique. In addition, we have proposed a novel gate splitting methodology to reduce delay variation in the ECO placement considering spatial correlations. Experimental results on benchmark circuits showed the effectiveness of our approaches

Inductance modeling for onchip interconnects

Abstract. As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization

Novel MRI Technologies for Structural and Functional Imaging of Tissues with Ultra-short T₂ Values

Conventional MRI has several limitations such as long scan durations, motion artifacts, very loud acoustic noise, signal loss due to short relaxation times, and RF induced heating of electrically conducting objects. The goals of this work are to evaluate and improve the state-of-the-art methods for MRI of tissue with short T₂, to prove the feasibility of in vivo Concurrent Excitation and Acquisition, and to introduce simultaneous electroglottography measurement during functional lung MRI

Modeling and Control of a 7-Level Switched Capacitor Rectifier for Wireless Power Transfer Systems

Wireless power continues to increase in popularity for consumer device charging. Rectifier characteristics like efficiency, compactness, impedance tunability, and harmonic content make the multi-level switched capacitor rectifier (MSC) an exceptional candidate for modern WPT systems. The MSC shares the voltage conversion characteristics of a post-rectification buck-boost topology, reduces waveform distortion via its multi-level modulation scheme, demonstrates tank tunability via the phase control inherent to actively switched rectifiers, and accomplishes all this without a bulky filter inductor. In this work, the MSC WPT system operation is explained, and a loss model is constructed. A prototype system is used to validate the models, showing exceptional agreement with the predicted efficiencies. The modeled MSC efficiencies are between 96.1% and 98.0% over the experimental power range up to 20.0 W. Two significant control loops are required for the MSC to be implemented in a real system. First, the output power is regulated using the modulation of the rectifier\u27s input voltage. Second, the switching frequency of the rectifier must exactly match the WPT carrier frequency set by the inverter on the primary side. Here, a small signal discrete time model is used to construct four transfer functions relating to the output voltage. Then, four novel time-to-time transfer functions are built on top of the discrete time model to inform the frequency synchronization feedback loop. Both loops are tested and validated in isolation. Finally, the dual-loop control problem is defined, closed form equations that include loop interactions are derived, and stable wide-range dual-loop operation is demonstrated experimentally

BioMEMS for cardiac tissue monitoring and maturation

Diseases of the heart have been the most common cause of death in the United States since the middle of the 20th century. The development of engineered cardiac tissue over the last three decades has yielded human induced pluripotent stem cell-derived (hiPSC) cardiomyocytes (CMs), microscale “heart-on-a-chip” platforms, optical interrogation techniques, and more. Having spawned its own scientific field, ongoing research promises lofty goals to address the heart disease burden around the world, such as patient-specific disease models, and clinical trials on chip-based platforms. The greatest academic pursuit for engineered cardiac tissues is to increase their maturity, thereby increasing relevance to native adult tissue. Investigation of cardiomyocyte maturity necessitates the development of 3D-tissue compatible techniques for measuring and perturbing cardiac biology with enhanced precision. This dissertation focuses on the development of biological microelectromechanical systems (BioMEMS) for precision measurement and perturbation of cardiac tissue. We discuss three unique approaches to interfacing MEMS-based tools with cardiac biology. The first is a high resolution magnetic sensor, which directly measures the spatial gradient of a magnetic field. This has an ideal application in magnetocardiography (MCG), as the flux of ions during cardiac contractions produces measurable magnetic signals around the tissue and can be leveraged for noncontact diagnosis. The second is a highly functionalized heart-on-a-chip platform, wherein the mechanical contractions of cardiac microtissues can be simultaneously recorded and actuated. Contractile dynamics are leading indicators of maturity in engineered cardiac tissue and mechanical conditioning has shown recent promise as a critical component of cardiac maturation. The third is the imaging of contractile nanostructures in engineered cardiomyocytes at depth in a 3D microtissue. We use small angle X-ray scattering (SAXS) to discern the periodic arrangement of myofilaments in their native 3D environment. We enable a significant structural analysis to provide insight for functional maturation. Enabling these three thrusts required developing two supporting technologies. The first is the engineered control of dynamic second order systems, a foundational element of all our MEMS and magnetic techniques. We demonstrate numerous algorithms to improve settling time or decrease dead-time such that samples with fast temporal effects can be measured. The second is a microscale gluing technique for integrating myriad of materials with MEMS devices, yielding unique sensors and actuators.2022-05-15T00:00:00

Learning-Based Hardware Design for Data Acquisition Systems

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conceptually allowing radically new device designs. The mathematical results in classical Compressive Sampling (CS) support the paradigm of Analog-to-Information Conversion (AIC) as a replacement for conventional ADC technologies. The AICs simultaneously perform data acquisition and compression, seeking to directly sample signals for achieving specific tasks as opposed to acquiring a full signal only at the Nyquist rate to throw most of it away via compression. Our contention is that in order for CS to live up its name, both theory and practice must leverage concepts from learning. This work demonstrates our contention in hardware prototypes, with key trade-offs, for two different fields of application as edge and big-data computing. In the framework of edge-data computing, such as wearable and implantable ecosystems, the power budget is defined by the battery capacity, which generally limits the device performance and usability. This is more evident in very challenging field, such as medical monitoring, where high performance requirements are necessary for the device to process the information with high accuracy. Furthermore, in applications like implantable medical monitoring, the system performances have to merge the small area as well as the low-power requirements, in order to facilitate the implant bio-compatibility, avoiding the rejection from the human body. Based on our new mathematical foundations, we built different prototypes to get a neural signal acquisition chip that not only rigorously trades off its area, energy consumption, and the quality of its signal output, but also significantly outperforms the state-of-the-art in all aspects. In the framework of big-data and high-performance computation, such as in high-end servers application, the RF circuits meant to transmit data from chip-to-chip or chip-to-memory are defined by low power requirements, since the heat generated by the integrated circuits is partially distributed by the chip package. Hence, the overall system power budget is defined by its affordable cooling capacity. For this reason, application specific architectures and innovative techniques are used for low-power implementation. In this work, we have developed a single-ended multi-lane receiver for high speed I/O link in servers application. The receiver operates at 7 Gbps by learning inter-symbol interference and electromagnetic coupling noise in chip-to-chip communication systems. A learning-based approach allows a versatile receiver circuit which not only copes with large channel attenuation but also implements novel crosstalk reduction techniques, to allow single-ended multiple lines transmission, without sacrificing its overall bandwidth for a given area within the interconnect's data-path