Variability-aware low-power techniques for nanoscale mixed-signal circuits.

New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored

Fast and Robust Design of CMOS VCO for Optimal Performance

The exponentially growing design complexity with technological advancement calls for a large scope in the analog and mixed signal integrated circuit design automation. In the automation process, performance optimization under different environmental constraints is of prime importance. The analog integrated circuits design strongly requires addressing multiple competing performance objectives for optimization with ability to find global solutions in a constrained environment. The integrated circuit (IC) performances are significantly affected by the device, interconnect and package parasitics. Inclusion of circuit parasitics in the design phase along with performance optimization has become a bare necessity for faster prototyping. Besides this, the fabrication process variations have a predominant effect on the circuit performance, which is directly linked to the acceptability of manufactured integrated circuit chips. This necessitates a manufacturing process tolerant design. The development of analog IC design methods exploiting the computational intelligence of evolutionary techniques for optimization, integrating the circuit parasitic in the design optimization process in a more meaningful way and developing process fluctuation tolerant optimal design is the central theme of this thesis. Evolutionary computing multi-objective optimization techniques such as Non-dominated Sorting Genetic Algorithm-II and Infeasibility Driven Evolutionary Algorithm are used in this thesis for the development of parasitic aware design techniques for analog ICs. The realistic physical and process constraints are integrated in the proposed design technique. A fast design methodology based on one of the efficient optimization technique is developed and an extensive worst case process variation analysis is performed. This work also presents a novel process corner variation aware analog IC design methodology, which would effectively increase the yield of chips in the acceptable performance window. The performance of all the presented techniques is demonstrated through the application to CMOS ring oscillators, current starved and xi differential voltage controlled oscillators, designed in Cadence Virtuoso Analog Design Environment

Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams

This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

SYNTHESIS AND EVALUATION OF ANTIMICROBIAL ACTIVITY OF PHENYL AND FURAN-2-YL[1,2,4] TRIAZOLO[4,3-a]QUINOXALIN-4(5H)-ONE AND THEIR HYDRAZONE PRECURSORS

A variety of 1-(s-phenyl)-[1,2,4]triazolo[4,3-a]quinoxalin-4(5H)-one (3a-3h) and 1-(s-furan-2-yl)-[1,2,4]triazolo[4,3- a]quinoxalin-4(5H)-one (5a-d) were synthesized from thermal annelation of corresponding hydrazones (2a-h) and (4a-d) respectively in the presence of ethylene glycol which is a high boiling solvent. The structures of the compounds prepared were confirmed by analytical and spectral data. Also, the newly synthesized compounds were evaluated for possible antimicrobial activity. 3-(2-(4-hydroxylbenzylidene)hydrazinyl)quinoxalin-2(1H)-one (2e) was the most active antibacterial agent while 1-(5-Chlorofuran-2-yl)-[1,2,4]triazolo[4,3-a]quinoxalin-4(5H)-one (5c) stood out as the most potent antifungal agent

Design Techniques of Energy Efficient PLL for Enhanced Noise and Lock Performance

Phase locked loops(PLLs)are vital building blocks of communication sys-tems whose performance dictates the quality of communication.The design of PLL to o_er superior performance is the prime objective of this research.It is desirable for the PLL to have fast locking,low noise,low reference spur,wide lock range,low power consumption consuming less silicon area.To achieve these performance parameters simultaneously in a PLL being a challenging task is taken up as a scope of the present work.A comprehensive study of the performance linked PLL components along with their design challenges is made in this report.The phase noise which is directly related to the dead zone of the PLL is minimized using an e_cient phase frequency detector(PFD)in this thesis.Here a voltage variable delay element is inserted in the reset path of the PFD to reduce the dead zone.An adaptive PFD architecture is also proposed to have a low noise and fast PLL simultaneously.In this work,before locking a fast PFD and in the locked state a low noise PFD operates to dictate the phase di_erence of the reference and feedback signals.To reduce the reference spur,a novel charge pump architecture is proposed which eventually reduces the lock time up to a great extent.In this charge pump a single current source is employed to reduce the output current mis-match and transmission gates are used to reduce the non ideal e_ects.Besides this,the fabrication process variations have a predominant e_ect on the PLL performance,which is directly linked to the locking capability.This necessitates a manufacturing process variation tolerant design of the PLL.In this work an e_cient multi-objective optimization method is also applied to at-tain multiple optimal performance objectives.The major performances under consideration are lock time,phase noise,lock range and power consumption

Low-power Wearable Healthcare Sensors

Advances in technology have produced a range of on-body sensors and smartwatches that can be used to monitor a wearer’s health with the objective to keep the user healthy. However, the real potential of such devices not only lies in monitoring but also in interactive communication with expert-system-based cloud services to offer personalized and real-time healthcare advice that will enable the user to manage their health and, over time, to reduce expensive hospital admissions. To meet this goal, the research challenges for the next generation of wearable healthcare devices include the need to offer a wide range of sensing, computing, communication, and human–computer interaction methods, all within a tiny device with limited resources and electrical power. This Special Issue presents a collection of six papers on a wide range of research developments that highlight the specific challenges in creating the next generation of low-power wearable healthcare sensors