Limitations of the classical phase-locked loop analysis

Nonlinear analysis of the classical phase-locked loop (PLL) is a challenging task. In classical engineering literature simplified mathematical models and simulation are widely used for its study. In this work the limitations of classical engineering phase-locked loop analysis are demonstrated, e.g., hidden oscillations, which can not be found by simulation, are discussed. It is shown that the use of simplified dynamical models and the application of simulation may lead to wrong conclusions concerning the operability of PLL-based circuits

A short survey on nonlinear models of the classic Costas loop: rigorous derivation and limitations of the classic analysis

Rigorous nonlinear analysis of the physical model of Costas loop --- a classic phase-locked loop (PLL) based circuit for carrier recovery, is a challenging task. Thus for its analysis, simplified mathematical models and numerical simulation are widely used. In this work a short survey on nonlinear models of the BPSK Costas loop, used for pre-design and post-design analysis, is presented. Their rigorous derivation and limitations of classic analysis are discussed. It is shown that the use of simplified mathematical models, and the application of non rigorous methods of analysis (e.g., simulation and linearization) may lead to wrong conclusions concerning the performance of the Costas loop physical model.Comment: Accepted to American Control Conference (ACC) 2015 (Chicago, USA

Limitations of PLL simulation: hidden oscillations in MatLab and SPICE

Nonlinear analysis of the phase-locked loop (PLL) based circuits is a challenging task, thus in modern engineering literature simplified mathematical models and simulation are widely used for their study. In this work the limitations of numerical approach is discussed and it is shown that, e.g. hidden oscillations may not be found by simulation. Corresponding examples in SPICE and MatLab, which may lead to wrong conclusions concerning the operability of PLL-based circuits, are presented

Hidden attractors in fundamental problems and engineering models

Recently a concept of self-excited and hidden attractors was suggested: an attractor is called a self-excited attractor if its basin of attraction overlaps with neighborhood of an equilibrium, otherwise it is called a hidden attractor. For example, hidden attractors are attractors in systems with no equilibria or with only one stable equilibrium (a special case of multistability and coexistence of attractors). While coexisting self-excited attractors can be found using the standard computational procedure, there is no standard way of predicting the existence or coexistence of hidden attractors in a system. In this plenary survey lecture the concept of self-excited and hidden attractors is discussed, and various corresponding examples of self-excited and hidden attractors are considered

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation

Investigation of high bandwith biodevices for transcutaneous wireless telemetry

PhD ThesisBIODEVICE implants for telemetry are increasingly applied today in various areas applications. There are many examples such as; telemedicine, biotelemetry, health care, treatments for chronic diseases, epilepsy and blindness, all of which are using a wireless infrastructure environment. They use microelectronics technology for diagnostics or monitoring signals such as Electroencephalography or Electromyography. Conceptually the biodevices are defined as one of these technologies combined with transcutaneous wireless implant telemetry (TWIT). A wireless inductive coupling link is a common way for transferring the RF power and data, to communicate between a reader and a battery-less implant. Demand for higher data rate for the acquisition data returned from the body is increasing, and requires an efficient modulator to achieve high transfer rate and low power consumption. In such applications, Quadrature Phase Shift Keying (QPSK) modulation has advantages over other schemes, and double the symbol rate with respect to Binary Phase Shift Keying (BPSK) over the same spectrum band. In contrast to analogue modulators for generating QPSK signals, where the circuit complexity and power dissipation are unsuitable for medical purposes, a digital approach has advantages. Eventually a simple design can be achieved by mixing the hardware and software to minimize size and power consumption for implantable telemetry applications. This work proposes a new approach to digital modulator techniques, applied to transcutaneous implantable telemetry applications; inherently increasing the data rate and simplifying the hardware design. A novel design for a QPSK VHDL modulator to convey a high data rate is demonstrated. Essentially, CPLD/FPGA technology is used to generate hardware from VHDL code, and implement the device which performs the modulation. This improves the data transmission rate between the reader and biodevice. This type of modulator provides digital synthesis and the flexibility to reconfigure and upgrade with the two most often languages used being VHDL and Verilog (IEEE Standard) being used as hardware structure description languages. The second objective of this thesis is to improve the wireless coupling power (WCP). An efficient power amplifier was developed and a new algorithm developed for auto-power control design at the reader unit, which monitors the implant device and keeps the device working within the safety regulation power limits (SAR). The proposed system design has also been modeled and simulated with MATLAB/Simulink to validate the modulator and examine the performance of the proposed modulator in relation to its specifications.Higher Education Ministry in Liby