A bibliography on digital computer-aided circuit analysis and design

Digital computer-aided electric logic circuit analysis and design bibliograph

Computer-aided circuit analysis Annual report, May 15, 1965 - May 14, 1966

Research on digital computer aided analysis of electric circuit

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area

Ultra-Low Power and Radiation Hardened Asynchronous Circuit Design

This dissertation proposes an ultra-low power design methodology called bit-wise MTNCL for bit-wise pipelined asynchronous circuits, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. It provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. It was enhanced to handle indeterminate standby states. The original MTNCL concept was enhanced significantly by sleeping Registers and Completion Logic as well as Combinational circuits to reduce area, leakage power, and energy per operation. This dissertation also develops an architecture that allows NCL circuits to recover from a Single Event Upset (SEU) or Single Event Latchup (SEL) fault without any data loss. Finally, an accurate throughput derivation formula for pipelined NCL circuits was developed, which can be used for static timing analysis

Cross-point architecture for spin transfer torque magnetic random access memory

Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture, which are difficult to surmount and few efficient design solutions have been reported in the literature. By using a STT-MRAM SPICE model including precise experimental parameters and STMicroelectronics 65 nm technology, some chip characteristic results such as cell area, data access speed and power have been calculated or simulated to demonstrate the expected performances of this new memory architecture

A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 [degrees] for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB

Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963

Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication

Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors

Thanks to aggressive scaling of transistor dimensions, computers have revolutionized our life. However, the increasing unreliability of devices fabricated in nanoscale technologies emerged as a major threat for the future success of computers. In particular, accelerated transistor aging is of great importance, as it reduces the lifetime of digital systems. This thesis addresses this challenge by proposing new methods to model, analyze and mitigate aging at microarchitecture-level and above