Development of MNOS technology Final report

Metal nitride oxide semiconductor structures for amplifying and memor

Nitrided La 2O 3 as charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of La 2O 3 with and without nitrogen incorporation were investigated based on Al/Al 2O 3/La 2O 3/SiO 2Si (MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction and X-ray photoelectron spectroscopy. Compared with the MONOS capacitor with La 2O 3 as charge-trapping layer, the one with nitrided La 2O 3 showed a larger memory window (4.9 V at ±10-V sweeping voltage), higher program speed (4.9 V at 1-ms +14 V), and smaller charge loss (27% after 10 years), due to the nitrided La 2O 3 film exhibiting less crystallized structure and high trap density induced by nitrogen incorporation, and suppressed leakage by nitrogen passivation. © 2012 IEEE.published_or_final_versio

Study of Charges Present in Silicon Nitride Thin Films and Their Effect on Silicon Solar Cell Efficiencies

abstract: As crystalline silicon solar cells continue to get thinner, the recombination of carriers at the surfaces of the cell plays an ever-important role in controlling the cell efficiency. One tool to minimize surface recombination is field effect passivation from the charges present in the thin films applied on the cell surfaces. The focus of this work is to understand the properties of charges present in the SiNx films and then to develop a mechanism to manipulate the polarity of charges to either negative or positive based on the end-application. Specific silicon-nitrogen dangling bonds (·Si-N), known as K center defects, are the primary charge trapping defects present in the SiNx films. A custom built corona charging tool was used to externally inject positive or negative charges in the SiNx film. Detailed Capacitance-Voltage (C-V) measurements taken on corona charged SiNx samples confirmed the presence of a net positive or negative charge density, as high as +/- 8 x 1012 cm-2, present in the SiNx film. High-energy (~ 4.9 eV) UV radiation was used to control and neutralize the charges in the SiNx films. Electron-Spin-Resonance (ESR) technique was used to detect and quantify the density of neutral K0 defects that are paramagnetically active. The density of the neutral K0 defects increased after UV treatment and decreased after high temperature annealing and charging treatments. Etch-back C-V measurements on SiNx films showed that the K centers are spread throughout the bulk of the SiNx film and not just near the SiNx-Si interface. It was also shown that the negative injected charges in the SiNx film were stable and present even after 1 year under indoor room-temperature conditions. Lastly, a stack of SiO2/SiNx dielectric layers applicable to standard commercial solar cells was developed using a low temperature (< 400 °C) PECVD process. Excellent surface passivation on FZ and CZ Si substrates for both n- and p-type samples was achieved by manipulating and controlling the charge in SiNx films.Dissertation/ThesisPh.D. Electrical Engineering 201

High dielectric constant materials in SONOS-type non- volatile memory structures

Ph.DDOCTOR OF PHILOSOPH

Tin dioxide nanoparticle based sensor integrated with microstrip antenna for passive wireless ethylene sensing

In this dissertation, we present the development and integration of a passive ethylene gas sensor with triangular microstrip patch antenna for wireless monitoring of climacteric fruit freshness. The existing ethylene sensors are mostly SnO2 resistor based active sensors, fabricated on rigid substrates requiring high fabrication temperatures and cannot be used for wireless applications. The proposed passive ethylene gas sensor is a novel nanoparticle based SnO2 capacitive sensor which, unlike the other existing SnO2resistor based active thick film and thin film sensors, consists of 10 nm to 15 nm SnO2 nanoparticles coated as a thin dielectric film of 1300 nm thickness. The nanoscale particle size and film thickness of the sensing dielectric layer in the capacitor model aids in sensing ethylene at room temperature and eliminates the need for micro hotplates used in existing SnO2 based resistive sensors. In comparison to the high sintering deposition temperatures used for many currently available ethylene sensors fabricated on rigid substrates, the SnO2 sensing layer is deposited using a room temperature dip coating process on flexible polyimide substrates. The capacitive sensor fabricated with pure SnO2 nanoparticles as the dielectric showed a 5 pF change in capacitance when ethylene gas concentration was increased from 0 to 100 ppm. The change in capacitance was increased to 7 pF by introducing a 10 nm layer of platinum (Pt) and palladium (Pd) alloy deposited by sputter deposition. This also improved the selectivity of the sensor to ethylene mixed in a CO2 gas environment. The response time was decreased to 3 min for SnO2 samples with Pt/Pd layer (5 min for pure SnO2samples) and its recovery time was decreased to 5 min compared to 7 min for pure SnO2 samples. The passive SnO2 capacitive ethylene sensor is integrated with a triangular microstrip patch antenna using capacitively loaded integration methodology which represents a one of a kind passive wireless sensor tag used for detecting freshness of climacteric fruit. The integration methodology adapted also reduced the size of the triangular patch antenna by 63 percent. The decrease in sensor capacitance due to the presence of ethylene (0 to 100 ppm) changes the antenna resonant frequency by 7 MHz and return loss by 9.5 dB, which makes the system reliable for far field wireless ethylene monitoring applications. The sensor tag output was also detected using an RFID reader showing a change in demodulated signal amplitude of 3 mV. Experimental result is presented for detecting multiple sensor tags at varying distances based on the wireless measurement of return loss which eliminates the common distance problem existing in backscatter signal based tags

A novel low-temperature growth method of silicon structures and application in flash memory.

Flash memories are solid-state non-volatile memories. They play a vital role especially in information storage in a wide range of consumer electronic devices and applications including smart phones, digital cameras, laptop computers, and satellite navigators. The demand for high density flash has surged as a result of the proliferation of these consumer electronic portable gadgets and the more features they offer – wireless internet, touch screen, video capabilities. The increase in the density of flash memory devices over the years has come as a result of continuous memory cell-size reduction. This size scaling is however approaching a dead end and it is widely agreed that further reduction beyond the 20 nm technological node is going to be very difficult, as it would result to challenges such as cross-talk or cell-to-cell interference, a high statistical variation in the number of stored electrons in the floating gate and high leakage currents due to thinner tunnel oxides. Because of these challenges a wide range of solutions in form of materials and device architectures are being investigated. Among them is three-dimensional (3-D) flash, which is widely acclaimed as the ideal solution, as they promise the integration of long-time retention and ultra-high density cells without compromising device reliability. However, current high temperature (>600 °C) growth techniques of the Polycrystalline silicon floating gate material are incompatible with 3-D flash memory; with vertically stacked memory layers, which require process temperatures to be ≤ 400 °C. There already exist some low temperature techniques for producing polycrystalline silicon such as laser annealing, solid-phase crystallization of amorphous silicon and metal-induced crystallization. However, these have some short-comings which make them not suitable for use in 3-D flash memory, e.g. the high furnace annealing temperatures (700 °C) in solid-phase crystallization of amorphous silicon which could potentially damage underlying memory layers in 3-D flash, and the metal contaminants in metal-induced crystallization which is a potential source of high leakage currents. There is therefore a need for alternative low temperature techniques that would be most suitable for flash memory purposes. With reference to the above, the main objective of this research was to develop a novel low temperature method for growing silicon structures at ≤ 400 °C. This thesis thus describes the development of a low-temperature method for polycrystalline silicon growth and the application of the technique in a capacitor-like flash memory device. It has been demonstrated that silicon structures with polycrystalline silicon-like properties can be grown at ≤ 400 °C in a 13.56 MHz radio frequency (RF) plasma-enhanced chemical vapour deposition (PECVD) reactor with the aid of Nickel Formate Dihydrate (NFD). It is also shown that the NFD coated on the substrates, thermally decomposes in-situ during the deposition process forming Ni particles that act as nucleation and growth sites of polycrystalline silicon. Silicon films grown by this technique and without annealing, have exhibited optical band gaps of ~ 1.2 eV compared to 1.78 eV for films grown under identical conditions but without the substrate being coated. These values were determined from UV-Vis spectroscopy and Tauc plots. These optical band gaps correspond to polycrystalline silicon and amorphous silicon respectively, meaning that the films grown on NFD-coated substrates are polycrystalline silicon while those grown on uncoated substrates remain amorphous. Moreover, this novel technique has been used to fabricate a capacitor-like flash memory that has exhibited hysteresis width corresponding to charge storage density in the order of 1012 cm-2 with a retention time well above 20 days for a device with silicon films grown at 300 °C. Films grown on uncoated films have not exhibit any significant hysteresis, and thus no flash memory-like behaviour. Given that all process temperatures throughout the fabrication of the devices are less than 400 °C and that no annealing of any sort was done on the material and devices, this growth method is thermal budget efficient and meets the crucial process temperature requirements of 3-D flash memory. Furthermore, the technique is glass compatible, which could prove a major step towards the acquisition of flash memory-integrated systems on glass, as well as other applications requiring low temperature polycrystalline silicon

A Novel Micro Piezoelectric Energy Harvesting System

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2007Bu tezde yeni bir titreşim temelli mikro enerji harmanlayıcı sistemi önerilmiştir. Titreşimler ve ani hareketler, mekanik yapının sadece eğilmesine değil aynı zamanda gerilmesine yol açar, bu sayede sistem doğrusal olmayan bölgede çalışır. İnce piezoelektrik film tabakası mekanik stresi elektrik enerjisine çevirir. Mikrowatt mertebesinde güç seviyeleri mm3’lük aletlerle elde edilebilir, bu da güneş panellerinde elde edilen güç yoğunlukları kadar yüksektir. Algılayıcı kabiliyeti sayesinde bilgi depolayabilen, kum tanesi büyüklüğünde olan ve üretiminde kullanılan temel malzeme silikon olan bu aletler “zeki kum” olarak isimlendirilmiştir. Mekanik yapının modellenmesi ve tasarımı geliştirilmiş ve üretim sonuçları da ayrıca verilmiştir. Sistemin bilgi gönderebilmesi ve alabilmesi amacıyla iyi bilinen RFID teknolojisi tabanlı bir kablosuz haberleşme yöntemi önerilmiştir. Bu bağlamda, paket taşımacılığında sürekli ivme denetleme, sınır güvenliği için kendinden beslemeli algılayıcılar, çabuk bozulan yiyeceklerin taşımacılığında sıcaklık denetleme ve pilsiz kalp atışı algılayıcı gibi birçok uygulama önerilmiştir.In this thesis, a novel, vibration based micro energy harvester system is proposed. Vibrations or sudden movements cause the mechanical structure does not only bend but also stretch, thus working in non-linear regime. The piezoelectric thin film layer converts the mechanical stress into the electrical energy. Microwatts of power can be achieved with a mm3 device which yields a high power density levels on the order of the solar panels. This device is named “smart sand”, because it has also sensor capabilities that can store information, its size is almost a sand grain and the main material used for the fabrication is silicon. The modeling and design of the mechanical structure has been developed and fabrication results have also been given in the thesis. In order for the system to send and receive the information, a wireless communication scheme is proposed which is based on the well-known RFID technology. In this concept, several applications are proposed such as continuous acceleration monitoring in package delivery, self-powered sensors for homeland security, temperature monitoring of the perishable food item delivery and a batteryless heart rate sensor.DoktoraPh

High performance floating gate memories using graphene as charge storage medium and atomic layer deposited high-k dielectric layers as tunnel barrier

Ankara : Materials Science and Nanotechnology Program of the Graduate School of Engineering and Science of Bilkent Univerity, 2013.Thesis (Master's) -- Bilkent University, 2013.Includes bibliographical references leaves 87-98.With the ongoing development in portable electronic devices, low power consumption, improved data retention rate and higher operation speed are the merits demanded by modern non-volatile memory technology. Flash memory devices with discrete charge-trapping media are regarded as an alternative solution to conventional floating gate technology. Flash memories utilizing Sinitride as charge storage media dominate due to enhanced endurance, better scaling capability and simple fabrication. The use of high-k dielectrics as tunnel layer and control layer is also crucial in charge-trap flash memory devices since they allow further scaling and enhanced charge injection without data retention degradation. Atomic layer deposition (ALD) is a powerful technique for the growth of pinhole-free high-k dielectrics with precisely controlled thickness and high conformality. The application of graphene as charge trapping medium in flash memory devices is promising to obtain improved charge storage capability with miniaturization. Graphene acts as an effective charge storage medium due to high density of states in deep energy levels. In this thesis, we fabricate graphene flash memory devices with ALD-grown HfO2/AlN as tunnel layer and Al2O3 as control layer. Graphene oxide nanosheets are derived from the acid exfoliation of natural graphite by Hummers Method. The graphene layer is obtained by spin-coating of water soluble graphene oxide suspension followed by a thermal annealing process. Memory performance including hysteresis window, data retention rate and program transient characteristics for both electron and hole storage mechanisms are determined by performing high frequency capacitance-voltage measurements. For comparing the memory effect of graphene on device performance, we also fabricate and characterize identical flash capacitors with Si-rich SiN layer as charge storage medium and HfO2 as tunnel oxide layer. The Si-nitride films are deposited with high SiH4/NH3 gas flow ratio by plasma-enhanced chemical vapor deposition system. Graphene flash memory devices exhibit superior memory performance. Compared with Si-nitride based cells, hysteresis window, retention performance and programming speed are both significantly enhanced with the use of graphene. For electron storage, graphene flash memory provides a saturated flat band shift of 1.2 V at a write-pulse duration of 100 ns with a voltage bias of 5 V. The high density of states and high work function of graphene improve the memory performance, leading to increased charge storage capability, enhanced retention rate and faster programming operation at low voltages. The use of graphene as charge storage medium and ALD-grown high-k dielectrics as tunnel and control layers improves the existing flash technology and satisfies the requirements including scalability, at least 10-year retention, low voltage operation, faster write performance and CMOS-compatible fabrication.Kocaay, DenizM.S

실리콘 기반의 전하 트랩 메모리를 이용한 시냅스의 가소성 및 학습 기능 구현

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 이종호.The development of an energy efficient and highly integrated electronic synapse is an important step in the effort to mimic the adaptive learning and memory in a biological neural network. Recently, several types of two-terminal memristors have been proposed to emulate biologically inspired synaptic functions using various components such as atomic switches, phase-change memory (PCM), and resistive switching devices. However, these two terminal devices require one select device per cell in a cell array to imitate a synapse-neuron network. Moreover, they need to be improved in terms of reliability, repeatability and processing complexity. In this thesis, we propose a new silicon-based charge trap memory device with an Al2O3/HfO2/Si3N4 (A/H/N) gate stack to realize the imitation of memory features in a biological synapse. In a fabricated capacitor having the proposed gate stack, short-term plasticity (STP) and long-term potentiation (LTP) properties with their transition are demonstrated, which are similar to the behavior of biological synapses. A single charge trapping layer (Si3N4) on silicon interface induces fast charge loss by trap-assisted tunneling (TAT) or direct tunneling. In addition, there is no remarkable pulse interval dependence when repeated input pulses are applied, in which the pulse amplitude and width are same. However, more frequent input pulses leads to larger current changes with longer retention property when HfO2 layer is inserted on Si3N4 layer as a second charge trapping layer. It is originated from the deep trap level (ET) in HfO2 layer leading to a transition into long-term memory. Lastly, we proposed a pair of pre- and post-synaptic spike scheme for the synaptic device and STDP property was demonstrated from experimental data. This suggested architecture has remarkable advantages, including high uniformity over a large area, excellent reliability, the use of CMOS-compatible materials, and easy integration with CMOS circuits.Chapter 1. Introduction 1 1.1 Motivation 1 1.2 Major factors influencing retention properties 2 1.3 Si3N4 and HfO2 for charge trap layers 5 1.4 Design of gate stack for synaptic device 7 1.5 Thesis organization 9 Chapter 2. Al2O3/HfO2/Si3N4 (A/H/N) gate stack 11 2.1 Introduction 11 2.2 Fabrication process for a capacitor 12 2.3 Measurement setup 14 2.4 C-V characteristics 15 2.5 Transient properties with C-t measurements 20 Chapter 3. Analysis of charge trapping and retention mechanism 30 3.1 Introduction 30 3.2 Measurement and discussion 31 Chapter 4. Synaptic characteristics in a FET device 41 4.1 Fabrication process of a FET device 41 4.2 Characteristics of SiO2/Si3N4 (O/N) stack 44 4.3 Scaling of Al2O3/HfO2/Si3N4 (A/H/N) stack 54 4.4 Spike-timing-dependent plasticity (STDP) 65 Chapter 5. Conclusions 70 Appendix. Spatial trap distribution near silicon interface 71 3.1 Introduction 71 3.2 Measurement results and discussion. 75 Bibliography 80 List of Publication 92 Abstract in Korean 94Docto