9,445 research outputs found
Simulation of Mixed Critical In-vehicular Networks
Future automotive applications ranging from advanced driver assistance to
autonomous driving will largely increase demands on in-vehicular networks. Data
flows of high bandwidth or low latency requirements, but in particular many
additional communication relations will introduce a new level of complexity to
the in-car communication system. It is expected that future communication
backbones which interconnect sensors and actuators with ECU in cars will be
built on Ethernet technologies. However, signalling from different application
domains demands for network services of tailored attributes, including
real-time transmission protocols as defined in the TSN Ethernet extensions.
These QoS constraints will increase network complexity even further.
Event-based simulation is a key technology to master the challenges of an
in-car network design. This chapter introduces the domain-specific aspects and
simulation models for in-vehicular networks and presents an overview of the
car-centric network design process. Starting from a domain specific description
language, we cover the corresponding simulation models with their workflows and
apply our approach to a related case study for an in-car network of a premium
car
Software-Defined Networks Supporting Time-Sensitive In-Vehicular Communication
Future in-vehicular networks will be based on Ethernet. The IEEE
Time-Sensitive Networking (TSN) is a promising candidate to satisfy real-time
requirements in future car communication. Software-Defined Networking (SDN)
extends the Ethernet control plane with a programming option that can add much
value to the resilience, security, and adaptivity of the automotive
environment. In this work, we derive a first concept for combining
Software-Defined Networking with Time-Sensitive Networking along with an
initial evaluation. Our measurements are performed via a simulation that
investigates whether an SDN architecture is suitable for time-critical
applications in the car. Our findings indicate that the control overhead of SDN
can be added without a delay penalty for the TSN traffic when protocols are
mapped properly.Comment: To be published at IEEE VTC2019-Sprin
Simulation and experimental evaluation of a flexible time triggered ethernet architecture applied in satellite nano/micro launchers
The success of small satellites has led to the study of new technologies for the realization of Nano and Micro Launch Vehicle (NMLV) in order to make competitive launch costs. The paper has the objective to define and experimentally investigate the performance of a communication system for NMLV interconnecting the End Systems as On-Board Computer (OBC), telemetry apparatus, Navigation Unit...we propose a low cost Ethernet-based solution able to provide the devices with high interconnection bandwidth. To guarantee hard delays to the Guide, Navigation and Control applications we propose some architectural changes of the traditional Ethernet network with the introduction of a layer implemented in the End Systems and allow for the lack of any contention on the network links. We show how the proposed solution has comparable performance to the one of TTEthernet standard that is a very expensive solution. An experimental test-bed equipped with Ethernet switches and Hercules boards by Texas Instruments is also provided to prove the feasibility of the proposed solution
Embedded Network Test-Bed for Validating Real-Time Control Algorithms to Ensure Optimal Time Domain Performance
The paper presents a Stateflow based network test-bed to validate real-time
optimal control algorithms. Genetic Algorithm (GA) based time domain
performance index minimization is attempted for tuning of PI controller to
handle a balanced lag and delay type First Order Plus Time Delay (FOPTD)
process over network. The tuning performance is validated on a real-time
communication network with artificially simulated stochastic delay, packet loss
and out-of order packets characterizing the network.Comment: 6 pages, 12 figure
BDAQ53, a versatile pixel detector readout and test system for the ATLAS and CMS HL-LHC upgrades
BDAQ53 is a readout system and verification framework for hybrid pixel
detector readout chips of the RD53 family. These chips are designed for the
upgrade of the inner tracking detectors of the ATLAS and CMS experiments.
BDAQ53 is used in applications where versatility and rapid customization are
required, such as in laboratory testing environments, test beam campaigns, and
permanent setups for quality control measurements. It consists of custom and
commercial hardware, a Python-based software framework, and FPGA firmware.
BDAQ53 is developed as open source software with both software and firmware
being hosted in a public repository.Comment: 6 pages, 6 figure
Validate implementation correctness using simulation: the TASTE approach
High-integrity systems operate in hostile environment and must guarantee a continuous operational state, even if unexpected events happen. In addition, these systems have stringent requirements that must be validated and correctly translated from high-level specifications down to code. All these constraints make the overall development process more time-consuming. This becomes especially complex because the number of system functions keeps increasing over the years.
As a result, engineers must validate system implementation and check that its execution conforms to the specifications. To do so, a traditional approach consists in a manual instrumentation of the implementation code to trace system activity while operating. However, this might be error-prone because modifications are not automatic and still made manually. Furthermore, such modifications may have an impact on the actual behavior of the system.
In this paper, we present an approach to validate a system implementation by comparing execution against simulation. In that purpose, we adapt TASTE, a set of tools that eases system development by automating each step as much as possible. In particular, TASTE automates system implementation from functional (system functions description with their properties – period, deadline, priority, etc.) and deployment(processors, buses, devices to be used) models.
We tailored this tool-chain to create traces during system execution. Generated output shows activation time of each task, usage of communication ports (size of the queues, instant of events pushed/pulled, etc.) and other relevant execution metrics to be monitored. As a consequence, system engineers can check implementation correctness by comparing simulation and execution metrics
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