Reusable modelling and simulation of flexible manufacturing for next generation semiconductor manufacturing facilities

Automated material handling systems (AMHS) in 300 mm semiconductor manufacturing facilities may need to evolve faster than expected considering the high performance demands on these facilities. Reusable simulation models are needed to cope with the demands of this dynamic environment and to deliver answers to the industry much faster. One vision for intrabay AMHS is to link a small group of intrabay AMHS systems, within a full manufacturing facility, together using what is called a Merge/Diverge link. This promises better operational performance of the AMHS when compared to operating two dedicated AMHS systems, one for interbay transport and the other for intrabay handling. A generic tool for modelling and simulation of an intrabay AMHS (GTIA-M&S) is built, which utilises a library of different blocks representing the different components of any intrabay material handling system. GTIA-M&S provides a means for rapid building and analysis of an intrabay AMHS under different operating conditions. The ease of use of the tool means that inexpert users have the ability to generate good models. Models developed by the tool can be executed with the merge/diverge capability enabled or disabled to provide comparable solutions to production demands and to compare these two different configurations of intrabay AMHS using a single simulation model. Finally, results from simulation experiments on a model developed using the tool were very informative in that they include useful decision making data, which can now be used to further enhance and update the design and operational characteristics of the intrabay AMHS

Production Scheduling

Generally speaking, scheduling is the procedure of mapping a set of tasks or jobs (studied objects) to a set of target resources efficiently. More specifically, as a part of a larger planning and scheduling process, production scheduling is essential for the proper functioning of a manufacturing enterprise. This book presents ten chapters divided into five sections. Section 1 discusses rescheduling strategies, policies, and methods for production scheduling. Section 2 presents two chapters about flow shop scheduling. Section 3 describes heuristic and metaheuristic methods for treating the scheduling problem in an efficient manner. In addition, two test cases are presented in Section 4. The first uses simulation, while the second shows a real implementation of a production scheduling system. Finally, Section 5 presents some modeling strategies for building production scheduling systems. This book will be of interest to those working in the decision-making branches of production, in various operational research areas, as well as computational methods design. People from a diverse background ranging from academia and research to those working in industry, can take advantage of this volume

Genetic Algorithm for Job Scheduling with Maintenance Consideration in Semiconductor Manufacturing Process

This paper presents wafer sequencing problems considering perceived chamber conditions and maintenance activities in a single cluster tool through the simulation-based optimization method. We develop optimization methods which would lead to the best wafer release policy in the chamber tool to maximize the overall yield of the wafers in semiconductor manufacturing system. Since chamber degradation will jeopardize wafer yields, chamber maintenance is taken into account for the wafer sequence decision-making process. Furthermore, genetic algorithm is modified for solving the scheduling problems in this paper. As results, it has been shown that job scheduling has to be managed based on the chamber degradation condition and maintenance activities to maximize overall wafer yield.open

BioFET-SIM Web Interface: Implementation and Two Applications

We present a web interface for the BioFET-SIM program. The web interface allows to conveniently setup calculations based on the BioFET-SIM multiple charges model. As an illustration, two case studies are presented. In the first case, a generic peptide with opposite charges on both ends is inverted in orientation on a semiconducting nanowire surface leading to a corresponding change in sign of the computed sensitivity of the device. In the second case, the binding of an antibody/antigen complex on the nanowire surface is studied in terms of orientation and analyte/nanowire surface distance. We demonstrate how the BioFET-SIM web interface can aid in the understanding of experimental data and postulate alternative ways of antibody/antigen orientation on the nanowire surface

Statistical Methods for Semiconductor Manufacturing

In this thesis techniques for non-parametric modeling, machine learning, filtering and prediction and run-to-run control for semiconductor manufacturing are described. In particular, algorithms have been developed for two major applications area: - Virtual Metrology (VM) systems; - Predictive Maintenance (PdM) systems. Both technologies have proliferated in the past recent years in the semiconductor industries, called fabs, in order to increment productivity and decrease costs. VM systems aim of predicting quantities on the wafer, the main and basic product of the semiconductor industry, that may be physically measurable or not. These quantities are usually ’costly’ to be measured in economic or temporal terms: the prediction is based on process variables and/or logistic information on the production that, instead, are always available and that can be used for modeling without further costs. PdM systems, on the other hand, aim at predicting when a maintenance action has to be performed. This approach to maintenance management, based like VM on statistical methods and on the availability of process/logistic data, is in contrast with other classical approaches: - Run-to-Failure (R2F), where there are no interventions performed on the machine/process until a new breaking or specification violation happens in the production; - Preventive Maintenance (PvM), where the maintenances are scheduled in advance based on temporal intervals or on production iterations. Both aforementioned approaches are not optimal, because they do not assure that breakings and wasting of wafers will not happen and, in the case of PvM, they may lead to unnecessary maintenances without completely exploiting the lifetime of the machine or of the process. The main goal of this thesis is to prove through several applications and feasibility studies that the use of statistical modeling algorithms and control systems can improve the efficiency, yield and profits of a manufacturing environment like the semiconductor one, where lots of data are recorded and can be employed to build mathematical models. We present several original contributions, both in the form of applications and methods. The introduction of this thesis will be an overview on the semiconductor fabrication process: the most common practices on Advanced Process Control (APC) systems and the major issues for engineers and statisticians working in this area will be presented. Furthermore we will illustrate the methods and mathematical models used in the applications. We will then discuss in details the following applications: - A VM system for the estimation of the thickness deposited on the wafer by the Chemical Vapor Deposition (CVD) process, that exploits Fault Detection and Classification (FDC) data is presented. In this tool a new clustering algorithm based on Information Theory (IT) elements have been proposed. In addition, the Least Angle Regression (LARS) algorithm has been applied for the first time to VM problems. - A new VM module for multi-step (CVD, Etching and Litography) line is proposed, where Multi-Task Learning techniques have been employed. - A new Machine Learning algorithm based on Kernel Methods for the estimation of scalar outputs from time series inputs is illustrated. - Run-to-Run control algorithms that employ both the presence of physical measures and statistical ones (coming from a VM system) is shown; this tool is based on IT elements. - A PdM module based on filtering and prediction techniques (Kalman Filter, Monte Carlo methods) is developed for the prediction of maintenance interventions in the Epitaxy process. - A PdM system based on Elastic Nets for the maintenance predictions in Ion Implantation tool is described. Several of the aforementioned works have been developed in collaborations with major European semiconductor companies in the framework of the European project UE FP7 IMPROVE (Implementing Manufacturing science solutions to increase equiPment pROductiVity and fab pErformance); such collaborations will be specified during the thesis, underlying the practical aspects of the implementation of the proposed technologies in a real industrial environment

Developing A Discrete-Event Simulation Model For Semiconductor Supply Chain

Due to the volatility of demand of integrated circuits (ICs), it is vital to have master planning activity for the manufacturing supply chain to forecast the demand. Production decisions and production planning are based on the demand forecast. With accurate forecasting result, the benefits could be found in the reduction of inventory cost, improvement of order fulfilment, high level of customer satisfaction and many more. In contrast, the most significant impact causes by bad demand forecast are waste of money and time. Specifically for fabless semiconductor company, the shorter duration between placing of sales order by customer and the order requested date compared to the manufacturing cycle time needed for the processes are the most significant challenge faced by the industry. The typical sales order is booked at eight to twelve weeks ahead of the order requested date. Whereas manufacturing cycle time for an end-to-end semiconductor process takes anywhere from 20 to 30 week. Therefore, by developing a discrete-event simulation model, some of the crucial decision variables such as the production quantities of products at different stages, the release quantity of bare wafer to the wafer fab, the amount of inventory of product and bare wafer at the end of a period could be examined in term of planning and control. The simulation model that is constructed in Python will have input parameters such as customers’ demand for product and GDPW (good die per wafer). The model is programmed with stock alarm to alert the user when the quantity of products reaches certain critical level, thus this model could help the company to control the process. On the other hand, the company could utilise the model to simulate the manufacturing activities when comes to planning. Through running the simulation, the company could get to know the duration needed to fulfil the customer’s demand and the level of inventory at each step to avoid high inventory holding costs due to overstocking

Algebraic level sets for CAD/CAE integration and moving boundary problems

Boundary representation (B-rep) of CAD models obtained from solid modeling kernels are commonly used in design, and analysis applications outside the CAD systems. Boolean operations between interacting B-rep CAD models as well as analysis of such multi-body systems are fundamental operations on B-rep geometries in CAD/CAE applications. However, the boundary representation of B-rep solids is, in general, not a suitable representation for analysis operations which lead to CAD/CAE integration challenges due to the need for conversion from B-rep to volumetric approximations. The major challenges include intermediate mesh generation step, capturing CAD features and associated behavior exactly and recurring point containment queries for point classification as inside/outside the solid. Thus, an ideal analysis technique for CAD/CAE integration that can enable direct analysis operations on B-rep CAD models while overcoming the associated challenges is desirable. ^ Further, numerical surface intersection operations are typically necessary for boolean operations on B-rep geometries during the CAD and CAE phases. However, for non-linear geometries, surface intersection operations are non-trivial and face the challenge of simultaneously satisfying the three goals of accuracy, efficiency and robustness. In the class of problems involving multi-body interactions, often an implicit knowledge of the boolean operation is sufficient and explicit intersection computation may not be needed. Such implicit boolean operations can be performed by point containment queries on B-rep CAD models. However, for complex non-linear B-rep geometries, the point containment queries may involve numerical iterative point projection operations which are expensive. Thus, there is a need for inexpensive, non-iterative techniques to enable such implicit boolean operations on B-rep geometries. ^ Moreover, in analysis problems with evolving boundaries (ormoving boundary problems), interfaces or cracks, blending functions are used to enrich the underlying domain with the known behavior on the enriching entity. The blending functions are typically dependent on the distance from the evolving boundaries. For boundaries defined by free form curves or surfaces, the distance fields have to be constructed numerically. This may require either a polytope approximation to the boundary and/or an iterative solution to determine the exact distance to the boundary. ^ In this work a purely algebraic, and computationally efficient technique is described for constructing signed distance measures from Non-Uniform Rational B-Splines (NURBS) boundaries that retain the geometric exactness of the boundaries while eliminating the need for iterative and non-robust distance calculation. The proposed technique exploits the NURBS geometry and algebraic tools of implicitization. Such a signed distance measure, also referred to as the Algebraic Level Sets, gives a volumetric representation of the B-rep geometry constructed by purely non-iterative algebraic operations on the geometry. This in turn enables both the implicit boolean operations and analysis operations on B-rep geometries in CAD/CAE applications. Algebraic level sets ensure exactness of geometry while eliminating iterative numerical computations. Further, a geometry-based analysis technique that relies on hierarchical partition of unity field compositions (HPFC) theory and its extension to enriched field modeling is presented. The proposed technique enables direct analysis of complex physical problems without meshing, thus, integrating CAD and CAE. The developed techniques are demonstrated by constructing algebraic level sets for complex geometries, geometry-based analysis of B-rep CAD models and a variety of fracture examples culminating in the analysis of steady state heat conduction in a solid with arbitrary shaped three-dimensional cracks. ^ The proposed techniques are lastly applied to investigate the risk of fracture in the ultra low-k (ULK) dies due to copper (Cu) wirebonding process. Maximum damage induced in the interlayer dielectric (ILD) stack during the process steps is proposed as an indicator of the reliability risk. Numerical techniques based on enriched isogeometric approximations are adopted to model damage in the ULK stacks using a cohesive damage description. A damage analysis procedure is proposed to conduct damage accumulation studies during Cu wirebonding process. Analysis is carried out to identify weak interfaces and potential sites for crack nucleation as well as damage nucleation patterns. Further, the critical process condition is identified by analyzing the damage induced during the impact and ultrasonic excitation stages. Also, representative ILD stack designs with varying Cu percentage are compared for risk of fracture

Intelligent shop scheduling for semiconductor manufacturing

Semiconductor market sales have expanded massively to more than 200 billion dollars annually accompanied by increased pressure on the manufacturers to provide higher quality products at lower cost to remain competitive. Scheduling of semiconductor manufacturing is one of the keys to increasing productivity, however the complexity of manufacturing high capacity semiconductor devices and the cost considerations mean that it is impossible to experiment within the facility. There is an immense need for effective decision support models, characterizing and analyzing the manufacturing process, allowing the effect of changes in the production environment to be predicted in order to increase utilization and enhance system performance. Although many simulation models have been developed within semiconductor manufacturing very little research on the simulation of the photolithography process has been reported even though semiconductor manufacturers have recognized that the scheduling of photolithography is one of the most important and challenging tasks due to complex nature of the process. Traditional scheduling techniques and existing approaches show some benefits for solving small and medium sized, straightforward scheduling problems. However, they have had limited success in solving complex scheduling problems with stochastic elements in an economic timeframe. This thesis presents a new methodology combining advanced solution approaches such as simulation, artificial intelligence, system modeling and Taguchi methods, to schedule a photolithography toolset. A new structured approach was developed to effectively support building the simulation models. A single tool and complete toolset model were developed using this approach and shown to have less than 4% deviation from actual production values. The use of an intelligent scheduling agent for the toolset model shows an average of 15% improvement in simulated throughput time and is currently in use for scheduling the photolithography toolset in a manufacturing plant

A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

In this article, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in the OFDM based IEEE 802.11a Wireless LAN (WLAN) baseband processor. The 64-point FFT is realized by decomposing it into a 2-D structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use any 2-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25 ?m BiCMOS technology. The core area of this chip is 6.8 mm2. The average dynamic power consumption is 41 mW @ 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i. e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption