Impact of converter interface type on the protection requirements for DC aircraft power systems

The utilization of converter interfaces has the potential to significantly alter the protection system design requirements in future aircraft platforms. However, the impact these converters will have can vary widely, depending on the topology of converter, its filter requirements and its control strategy. This means that the precise impact on the network fault response is often difficult to quantify. Through the analysis of example converter topologies and literature on the protection of DC networks, this paper tackles this problem by identifying key design characteristics of converters which influence their fault response. Using this information, the converters are classified based on their general fault characteristics, enabling potential protection issues and solutions to be readily identified. Finally, the paper discusses the potential for system level design benefits through the optimisation of converter topology and protection system design

Comprehensive and modular stochastic modeling framework for the variability-aware assessment of Signal Integrity in high-speed links

This paper presents a comprehensive and modular modeling framework for stochastic signal integrity analysis of complex high-speed links. Such systems are typically composed of passive linear networks and nonlinear, usually active, devices. The key idea of the proposed contribution is to express the signals at the ports of each of such system elements or subnetworks as a polynomial chaos expansion. This allows one to compute, for each block, equivalent deterministic models describing the stochastic variations of the network voltages and currents. Such models are synthesized into SPICE-compatible circuit equivalents, which are readily connected together and simulated in standard circuit simulators. Only a single circuit simulation of such an equivalent network is required to compute the pertinent statistical information of the entire system, without the need of running a large number of time-consuming electromagnetic circuit co-simulations. The accuracy and efficiency of the proposed approach, which is applicable to a large class of complex circuits, are verified by performing signal integrity investigations of two interconnect examples

Novel 600 V Low Reverse Recovery Loss Vertical PiN Diode with Hole Pockets by Bosch Deep Trench

The performance of a novel diode with characteristic trench shape is predicted by TCAD simulation. A novel 600 V vertical PiN diode with hole pockets by the Bosch deep trench process is proposed for a better trade-off curve between reverse recovery loss and forward voltage. The reverse recovery loss is reduced to a half. In addition, the active chip size of the novel diode is reduced to two-thirds that of the conventional PiN diode in the same forward voltage. The novel diode structure is a strong candidate when the simple fabrication process under development is established.ISPSD 2016 28th International Symposium on Power Semiconductor Devices and ICs., Jun 12-16, 2016, Žofín Palace, Prague, Czech Republi

Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection

High-performance vertical Si PiN diode by hole remaining mechanism

A novel diode with a unique trench shape is predicted by TCAD simulation to have high performance. The novel 600 V vertical PiN diode with hole pockets by the Bosch deep trench process shows a better trade-off curve between reverse recovery loss and forward voltage. The reverse recovery loss is reduced by half. In addition, the active chip size of the novel diode is reduced to two-thirds that of the conventional PiN diode in the same forward voltage. Thanks to the hole pockets with an electric field in the diagonal direction, the remaining hole suppresses the surge voltage with noise for high performance. In this paper, we specially focus on the analysis of phenomenon and the noise suppression mechanism during reverse recovery. The novel diode structure is a strong candidate when developing the fabrication process after silicon trench etching is established

Ultrafast Lateral 600 V Silicon SOI PiN Diode with Geometric Traps for Preventing Waveform Oscillation

An ultrafast lateral silicon PiN diode with traps is proposed using a silicon-on-insulator (SOI) substrate with traps. The proposed diode successfully suppresses waveform oscillation because the trapped hole suppresses electric field penetration and prevents the oscillation trigger known as “dynamic punch-through.” Because of the short current path caused by the oscillation prevention, the reverse recovery speed was higher and the reverse recovery loss was strongly reduced. The proposed trap structure and design method would contribute to performance improvement of all power semiconductor devices including IGBTs and power MOSFETs

Ultra-fast Lateral 600 V Silicon PiN Diode Superior to SiC-SBD

2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), Jun 15-19, 2014, Hilton Waikoloa Village, Hawaii, USAUltra-fast silicon PiN diode is proposed by lateral structure with traps using silicon on insulator (SOI) substrate as shown in Fig. 1. The proposed lateral SOI silicon PiN diode achieved ultra-fast reverse recovery without waveform oscillation successfully. The proposed lateral SOI structure with traps will contributes to performance improvement of all of bipolar power devices including IGBT

Modular multilevel converter based LCL DC/DC converter for high power DC transmission grids

This paper presents a modular multilevel converter (MMC) based DC/DC converter with LCL inner circuit for HVDC transmission and DC grids. Three main design challenges are addressed. The first challenge is the use of MMCs with higher operating frequency compared to common transformer-based DC/DC converters where MMC operating frequency is limited to a few hundred hertz due to core losses. The second issue is the DC fault response. With the LCL circuit, the steady state fault current is limited to a low magnitude which is tolerable by MMC semiconductors. Mechanical DC circuit breakers can therefore be used to interrupt fault current for permanent faults and extra sub-module bypass thyristors are not necessary to protect antiparallel diodes. Thirdly, a novel controller structure is introduced with multiple coordinate frames ensuring zero local reactive power at both bridges in the whole load range. The proposed controller structure is also expandable to a DC hub with multiple ports. Detailed simulations using PSCAD/EMTDC are performed to verify the aforementioned design solutions in normal and fault conditions

Modeling of Ultra Low Capacitance Transient Voltage Suppression Diode for High ESD Protection

To improve key properties such as ultra-low capacitance (ULC) and high-voltage (HV) breakdown, we have performed a simulation work about transient voltage suppression (TVS) diodes. ULC-TVS diode was designed to employ a double deep trench to cut off the various parasitic effects that may degrade the device performance. The electrostatic discharge (ESD) protection is the targeting for the best applications in high-frequency and high-speed ICs. In this work, the device could present excellent performance in terms of very responsive ESD properties, high breakdown voltage, low leakage current, and very low capacitance level. The double trenches are aligned to the top electrode contact to restrict field crowding effects by the strong electric field intensity. The performance would be sufficient for the robust ESD nature up to IEC61000-4-2 (30 kV) and compatible with strong surge protection IEC61000-4-5 (10A). Their electrical properties have been evaluated for structure from simulation and the results are obtained at the device parameters. Several process of device design related effects on the electrical capability and can be optimized. Keywords: ULC-TVS diode, simulation (TCAD), characteristics, capacitance, ESD protection

Novel 600 V Low Reverse Recovery Loss Vertical PiN Diode with Hole Pockets by Bosch Deep Trench

ISPSD 2016 28th International Symposium on Power Semiconductor Devices and ICs., Jun 12-16, 2016, Žofín Palace, Prague, Czech RepublicThe performance of a novel diode with characteristic trench shape is predicted by TCAD simulation. A novel 600 V vertical PiN diode with hole pockets by the Bosch deep trench process is proposed for a better trade-off curve between reverse recovery loss and forward voltage. The reverse recovery loss is reduced to a half. In addition, the active chip size of the novel diode is reduced to two-thirds that of the conventional PiN diode in the same forward voltage. The novel diode structure is a strong candidate when the simple fabrication process under development is established