2,981 research outputs found

    Replica determinism and flexible scheduling in hard real-time dependable systems

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    Fault-tolerant real-time systems are typically based on active replication where replicated entities are required to deliver their outputs in an identical order within a given time interval. Distributed scheduling of replicated tasks, however, violates this requirement if on-line scheduling, preemptive scheduling, or scheduling of dissimilar replicated task sets is employed. This problem of inconsistent task outputs has been solved previously by coordinating the decisions of the local schedulers such that replicated tasks are executed in an identical order. Global coordination results either in an extremely high communication effort to agree on each schedule decision or in an overly restrictive execution model where on-line scheduling, arbitrary preemptions, and nonidentically replicated task sets are not allowed. To overcome these restrictions, a new method, called timed messages, is introduced. Timed messages guarantee deterministic operation by presenting consistent message versions to the replicated tasks. This approach is based on simulated common knowledge and a sparse time base. Timed messages are very effective since they neither require communication between the local scheduler nor do they restrict usage of on-line flexible scheduling, preemptions and nonidentically replicated task sets

    Symmetrical clock synchronization with time-correlated photon pairs

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    We demonstrate a point-to-point clock synchronization protocol based on bidirectionally exchanging photons produced in spontaneous parametric down conversion (SPDC). The technique exploits tight timing correlations between photon pairs to achieve a precision of 51ps in 100s with count rates of order 200s−1^{-1}. The protocol is distance independent, secure against symmetric delay attacks and provides a natural complement to techniques based on Global Navigation Satellite Systems (GNSS). The protocol works with mobile parties and can be augmented to provide authentication of the timing signal via a Bell inequality check.Comment: 5 pages, 5 figure

    A clock synchronization skeleton based on RTAI

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    This paper presents a clock synchronization skeleton based on RTAI (Real Time Application Interface). The skeleton is a thin layer that provides unified but extendible interfaces to the underlying operating system, the synchronization algorithms and the upper level applications in need of clock synchronization. The skeleton provides synchronization support to a system, whereby the achieved accuracy is the best obtainable given this software structure. By connecting an algorithm and a communication module with the skeleton, a system becomes capable to run with synchronization support. To demonstrate and validate the design, the skeleton has been tested successfully with two different synchronization algorithms based on the CAN bus. Other algorithms and communication technologies can also work with the skeleton, as long as they provide the necessary functionalities for clock synchronization

    On Time Synchronization Issues in Time-Sensitive Networks with Regulators and Nonideal Clocks

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    Flow reshaping is used in time-sensitive networks (as in the context of IEEE TSN and IETF Detnet) in order to reduce burstiness inside the network and to support the computation of guaranteed latency bounds. This is performed using per-flow regulators (such as the Token Bucket Filter) or interleaved regulators (as with IEEE TSN Asynchronous Traffic Shaping). Both types of regulators are beneficial as they cancel the increase of burstiness due to multiplexing inside the network. It was demonstrated, by using network calculus, that they do not increase the worst-case latency. However, the properties of regulators were established assuming that time is perfect in all network nodes. In reality, nodes use local, imperfect clocks. Time-sensitive networks exist in two flavours: (1) in non-synchronized networks, local clocks run independently at every node and their deviations are not controlled and (2) in synchronized networks, the deviations of local clocks are kept within very small bounds using for example a synchronization protocol (such as PTP) or a satellite based geo-positioning system (such as GPS). We revisit the properties of regulators in both cases. In non-synchronized networks, we show that ignoring the timing inaccuracies can lead to network instability due to unbounded delay in per-flow or interleaved regulators. We propose and analyze two methods (rate and burst cascade, and asynchronous dual arrival-curve method) for avoiding this problem. In synchronized networks, we show that there is no instability with per-flow regulators but, surprisingly, interleaved regulators can lead to instability. To establish these results, we develop a new framework that captures industrial requirements on clocks in both non-synchronized and synchronized networks, and we develop a toolbox that extends network calculus to account for clock imperfections.Comment: ACM SIGMETRICS 2020 Boston, Massachusetts, USA June 8-12, 202

    A scalable line-independent design algorithm for voltage and frequency control in AC islanded microgrids

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    We propose a decentralized control synthesis procedure for stabilizing voltage and frequency in AC Islanded microGrids (ImGs) composed of Distributed Generation Units (DGUs) and loads interconnected through power lines. The presented approach enables Plug-and-Play (PnP) operations, meaning that DGUs can be added or removed without compromising the overall ImG stability. The main feature of our approach is that the proposed design algorithm is line-independent. This implies that (i) the synthesis of each local controller requires only the parameters of the corresponding DGU and not the model of power lines connecting neighboring DGUs, and (ii) whenever a new DGU is plugged in, DGUs physically coupled with it do not have to retune their regulators because of the new power line connected to them. Moreover, we formally prove that stabilizing local controllers can be always computed, independently of the electrical parameters. Theoretical results are validated by simulating in PSCAD the behavior of a 10-DGUs ImG
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