Improve the Usability of Polar Codes: Code Construction, Performance Enhancement and Configurable Hardware

Error-correcting codes (ECC) have been widely used for forward error correction (FEC) in modern communication systems to dramatically reduce the signal-to-noise ratio (SNR) needed to achieve a given bit error rate (BER). Newly invented polar codes have attracted much interest because of their capacity-achieving potential, efficient encoder and decoder implementation, and flexible architecture design space.This dissertation is aimed at improving the usability of polar codes by providing a practical code design method, new approaches to improve the performance of polar code, and a configurable hardware design that adapts to various specifications. State-of-the-art polar codes are used to achieve extremely low error rates. In this work, high-performance FPGA is used in prototyping polar decoders to catch rare-case errors for error-correcting performance verification and error analysis. To discover the polarization characteristics and error patterns of polar codes, an FPGA emulation platform for belief-propagation (BP) decoding is built by a semi-automated construction flow. The FPGA-based emulation achieves significant speedup in large-scale experiments involving trillions of data frames. The platform is a key enabler of this work. The frozen set selection of polar codes, known as bit selection, is critical to the error-correcting performance of polar codes. A simulation-based in-order bit selection method is developed to evaluate the error rate of each bit using Monte Carlo simulations. The frozen set is selected based on the bit reliability ranking. The resulting code construction exhibits up to 1 dB coding gain with respect to the conventional bit selection. To further improve the coding gain of BP decoder for low-error-rate applications, the decoding error mechanisms are studied and analyzed, and the errors are classified based on their distinct signatures. Error detection is enabled by low-cost CRC concatenation, and post-processing algorithms targeting at each type of the error is designed to mitigate the vast majority of the decoding errors. The post-processor incurs only a small implementation overhead, but it provides more than an order of magnitude improvement of the error-correcting performance. The regularity of the BP decoder structure offers many hardware architecture choices. Silicon area, power consumption, throughput and latency can be traded to reach the optimal design points for practical use cases. A comprehensive design space exploration reveals several practical architectures at different design points. The scalability of each architecture is also evaluated based on the implementation candidates. For dynamic communication channels, such as wireless channels in the upcoming 5G applications, multiple codes of different lengths and code rates are needed to t varying channel conditions. To minimize implementation cost, a universal decoder architecture is proposed to support multiple codes through hardware reuse. A 40nm length- and rate-configurable polar decoder ASIC is demonstrated to fit various communication environments and service requirements.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/140817/1/shuangsh_1.pd

Sum-α Stopping Criterion for Turbo Decoding

In this article, we propose a new stopping criterion for turbo codes. This criterion is based on the behaviour of the probabilistic values alpha 'α' calculated in the forward recursion during turbo decoding. We called this criterion Sum-α. The simulation results show that the Bit Error Rates BER are very close to those of the Cross-Entropy CE criterion with the same average number of iterations

Optimizing the Decoding Complexity of PEG-Based Methods with an Improved Hybrid Iterative/Gaussian Elimination Decoding Algorithm

This paper focuses on optimizing the decoding complexity of the progressive-edge-growth-based (PEG-based) method for the extended grouping of radio frequency identification (RFID) tags using a hybrid iterative/Gaussian elimination decoding algorithm. To further reduce the decoding time, the hybrid decoding is improved by including an early stopping criterion to avoid unnecessary iterations of iterative decoding for undecodable blocks. Various simulations have been carried out to analyse and assess the performance achieved with the PEG-based method under the improved hybrid decoding, both in terms of missing recovery capabilities and decoding complexities. Simulation results are presented, demonstrating that the improved hybrid decoding achieves the optimal missing recovery capabilities of full Gaussian elimination decoding at a lower complexity, as some of the missing tag identifiers are recovered iteratively

Application of integer quadratic programming in detection of high-dimensional wireless systems

High-dimensional wireless systems have recently generated a great deal of interest due to their ability to accommodate increasing demands for high transmission data rates with high communication reliability. Examples of such large-scale systems include single-input, single-output symbol spread OFDM system, large-scale single-user multi-input multi-output (MIMO) OFDM systems, and large-scale multiuser MIMO systems. In these systems, the number of symbols required to be jointly detected at the receiver is relatively large. The challenge with the practical realization of these systems is to design a detection scheme that provides high communication reliability with reasonable computational complexity, even as the number of simultaneously transmitted independent communication signals becomes very large.^ Most of the optimal or near-optimal detection techniques that have been proposed in the literature of relatively low-dimensional wireless systems, such as MIMO systems in which number of antennas is less than 10, become problematic for high-dimensional detection problems. That is, their performance degrades or the computational complexity becomes prohibitive, especially when higher-order QAM constellations are employed.^ In the first part of this thesis, we propose a near-optimal detection technique which offers a flexible trade-off between complexity and performance. The proposed technique formulates the detection problem in terms of Integer Quadratic Programming (IQP), which is then solved through a controlled Branch and Bound (BB) search tree algorithm. In addition to providing good performance, an important feature of this approach is that its computational complexity remains roughly the same even as we increase the constellation order from 4-QAM to 256-QAM. The performance of the proposed algorithm is investigated for both symbol spread OFDM systems and large-scale MIMO systems with both frequency selective and at fading channels.^ The second part of this work focuses on a reduced complexity version of IQP referred to as relaxed quadratic programming (QP). In particular, QP is used to reformulate two widely used detection schemes for MIMO OFDM: (1) Successive Interference Cancellation (SIC) and (2) Iterative Detecting and Decoding (IDD). First, SIC-based algorithms are derived via a QP formulation in contrast to using a linear MMSE detector at each stage. The resulting QP-SIC algorithms offer lower computational complexity than the SIC schemes that employ linear MMSE at each stage, especially when the dimension of the received signal vector is high. Three versions of QP-SIC are proposed based on various trade-offs between complexity and receiver performance; each of the three QP-SIC algorithms outperforms existing SIC techniques. Second, IDD-based algorithms are developed using a QP detector. We show how the soft information, in terms of the Log Likelihood Ratio (LLR), can be extracted from the QP detector. Further, the procedure for incorporating the a-priori information that is passed from the channel decoder to the QP detector is developed. Simulation results are presented demonstrating that the use of QP in IDD offers improved performance at the cost of a reasonable increase in complexity compared to linear detectors

A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS

In this paper we present an efficient system-on-chip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable data path and can be dynamically reconfigured to support multiple 4G standards. We utilize a pipelined version of the layered belief propagation algorithm to achieve partial-parallel decoding of structured LDPC codes. Instead of using the sub-optimal Minsum algorithm, we propose to use the powerful belief propagation (BP) decoding algorithm by designing an area-efficient soft-input soft-output (SISO) decoder. Two power saving schemes are employed to reduce the power consumption up to 65%. The decoder has been synthesized, placed, and routed on a TSMC 90nm 1.0V 8-metal layer CMOS technology with a total area of 3.5 mm2. The maximum clock frequency is 450 MHz and the estimated peak power consumption is 410 mW.NokiaNational Science Foundatio