Language Mechanisms for Controlling and Mitigating Timing Channels

We propose a new language-based approach to mitigating timing channels. In this language, well-typed programs provably leak only a bounded amount of information over time through external timing channels. By incorporating mechanisms for predictive mitigation of timing channels, this approach also permits a more expressive programming model. Timing channels arising from interaction with underlying hardware features such as instruction caches are controlled. Assumptions about the underlying hardware are explicitly formalized, supporting the design of hardware that efficiently controls timing channels. One such hardware design is modeled and used to show that timing channels can be controlled in some simple programs of real-world significance.This work has been supported by a grant from the Office of Naval Research (ONR N000140910652), by two grants from the NSF: 0424422 (the TRUST center), and 0964409, and by MURI grant FA9550-12-1-0400, administered by the US Air Force. This research is also sponsored by the Air Force Research Laboratory

Analysis of the intraspinal calcium dynamics and its implications on the plasticity of spiking neurons

The influx of calcium ions into the dendritic spines through the N-metyl-D-aspartate (NMDA) channels is believed to be the primary trigger for various forms of synaptic plasticity. In this paper, the authors calculate analytically the mean values of the calcium transients elicited by a spiking neuron undergoing a simple model of ionic currents and back-propagating action potentials. The relative variability of these transients, due to the stochastic nature of synaptic transmission, is further considered using a simple Markov model of NMDA receptos. One finds that both the mean value and the variability depend on the timing between pre- and postsynaptic action-potentials. These results could have implications on the expected form of synaptic-plasticity curve and can form a basis for a unified theory of spike time-dependent, and rate based plasticity.Comment: 14 pages, 10 figures. A few changes in section IV and addition of a new figur

The SST Fully-Synchronous Multi-GHz Analog Waveform Recorder with Nyquist-Rate Bandwidth and Flexible Trigger Capabilities

The design and performance of a fully-synchronous multi-GHz analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. The SST's objective is to provide multi-GHz sample rates with intrinsically-stable timing, Nyquist-rate sampling and high trigger bandwidth, wide dynamic range and simple operation. Containing 4 channels of 256 samples per channel, the SST is fabricated in an inexpensive 0.25 micrometer CMOS process and uses a high-performance package that is 8 mm on a side. It has a 1.9V input range on a 2.5V supply, exceeds 12 bits of dynamic range, and uses ~128 mW while operating at 2 G-samples/s and full trigger rates. With a standard 50 Ohm input source, the SST exceeds ~1.5 GHz -3 dB bandwidth. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator running at half the sample rate (e.g., a 1 GHz oscillator yields 2 G-samples/s). Because of its purely-digital synchronous nature, the SST has ps-level timing uniformity that is independent of sample frequencies spanning over 6 orders of magnitude: from under 2 kHz to over 2 GHz. Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. When operating as common-stop device, the time of the stop, modulo 256 relative to the start, is read out along with the sampled signal values. Each of the four channels integrates dual-threshold trigger circuitry with windowed coincidence features. Channels can discriminate signals with ~1mV RMS resolution at >600 MHz bandwidth.Comment: 3 pages, 6 figures, 1 table, submitted for publication in the Conference Record of the 2014 IEEE Nuclear Science Symposium, Seattle, WA, November 201

Building real-time embedded applications on QduinoMC: a web-connected 3D printer case study

Single Board Computers (SBCs) are now emerging with multiple cores, ADCs, GPIOs, PWM channels, integrated graphics, and several serial bus interfaces. The low power consumption, small form factor and I/O interface capabilities of SBCs with sensors and actuators makes them ideal in embedded and real-time applications. However, most SBCs run non-realtime operating systems based on Linux and Windows, and do not provide a user-friendly API for application development. This paper presents QduinoMC, a multicore extension to the popular Arduino programming environment, which runs on the Quest real-time operating system. QduinoMC is an extension of our earlier single-core, real-time, multithreaded Qduino API. We show the utility of QduinoMC by applying it to a specific application: a web-connected 3D printer. This differs from existing 3D printers, which run relatively simple firmware and lack operating system support to spool multiple jobs, or interoperate with other devices (e.g., in a print farm). We show how QduinoMC empowers devices with the capabilities to run new services without impacting their timing guarantees. While it is possible to modify existing operating systems to provide suitable timing guarantees, the effort to do so is cumbersome and does not provide the ease of programming afforded by QduinoMC.http://www.cs.bu.edu/fac/richwest/papers/rtas_2017.pdfAccepted manuscrip

A robust timing and frequency synchronization for OFDM systems

Abstract—A robust symbol-timing and carrier-frequency synchronization scheme applicable to orthogonal frequency-division-multiplexing systems is presented. The proposed method is based on a training symbol specifically designed to have a steep rolloff timing metric. The proposed timing metric also provides a robust sync detection capability. Both time domain training and frequency domain (FD) training are investigated. For FD training, maintaining a low peak-to-average power ratio of the training symbol was taken into consideration. The channel estimation scheme based on the designed training symbol was also incorporated in the system in order to give both fine-timing and frequency-offset estimates. For fine frequency estimation, two approaches are presented. The first one is based on the suppression of the interference introduced in the frequency estimation process by the training symbol pattern in the context of multipath dispersive channels. The second one is based on the maximum likelihood principle and does not suffer from any interference. A new performance measure is introduced for timing estimation, which is based on the plot of signal to timing-error-induced average interference power ratio against the timing estimate shift. A simple approach for finding the optimal setting of the timing estimator is presented. Finally, the sync detection, timing estimation, frequency estimation, and bit-error-rate performance of the proposed method are presented in a multipath Rayleigh fading channel. Index Terms—Frequency-offset estimation, orthogonal frequency-division multiplexing (OFDM), symbol-timing estimation, synchronization, training symbol. I