Nonvolatile CMOS memristor, reconfigurable array and its application in power load forecasting

© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/TII.2023.3341256The high cost, low yield, and low stability of nano-materials significantly hinder the application and development of memristors. To promote the application of memristors, researchers proposed a variety of memristor emulators to simulate memristor functions and apply them in various fields. However these emulators lack nonvolatile characteristics, limiting their scope of application. This paper proposes an innovative nonvolatile memristor circuit based on complementary metal-oxide-semiconductor (CMOS) technology, expanding the horizons of memristor emulators. The proposed memristor is fabricated in a reconfigurable array architecture using the standard CMOS process, allowing the connection between memristors to be altered by configuring the on-off state of switches. Compared to nano-material memristors, the CMOS nonvolatile memristor circuit proposed in this paper offers advantages of low manufacturing cost and easy mass production, which can promote the application of memristors. The application of the reconfigurable array is further studied by constructing an Echo State Network (ESN) for short-term load forecasting in the power system.Peer reviewe

Fully CMOS Memristor Based Chaotic Circuit

This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications

Memcapacitors

Mestrado em Engenharia Eletrónica e TelecomunicaçõesThe present work aims to continue the study of memory devices, initiated with the prediction of the existence of memristors by Leon Chua in 1971, with the study and characterization of memcapacitors as a semiconductor two-terminal device, characterized by the non-linear relation between charge and voltage, which also present the ability to remember the voltage or charge that passes through the device, graphically represented by a graphic with hysteresis characteristics, also presenting a variable capacitance in function of the charge applied in its terminals. Here, a characterizationof the response functions to a sinusoidal periodic input with variable frequency to three mathematical models of memcapacitive systems is performed: given a memcapacitor in series with an ac input voltage source, the respective hysteresis charge-voltage plots are studied by simulations in the MATLAB environment. Next, a classification of the hysteresis plots in function of its geometry is performed, given that the crossing of such graph in the (0.0) point defines it as a type I or type II hysteresis loop. The analysis continues with the morphological identification of the area of the hysteresis curve of the first model, by varying amplitude and frequency of the input source, in such a way to compare the other models with the ideal one, as well as to take the critical frequencis from which the memcapacitance becomes constant, and thus the system becomes linear, by making the hysteresis curve to become a straight line. The area of the first model was taken by calculations with the Green theorem.O presente trabalho propõe-se a continuar o estudo dos dispositivos de memória, iniciado com a predição dos memristors por Leon Chua em 1971, por meio do estudo e caracterização dos memcapacitores como dispositivos semicondutores de dois terminais, caracterizados pela relação não linear entre carga e tensão, que apresentam capacidade de recordar a tensão ou corrente que passa pelo dispositivo, graficamente representado em forma de um gráfico com características de histerese, aprensentando também capacitância variável em função da carga aplicada em seus terminais. Aqui, uma caracterização das funções de resposta a uma entrada periódica sinusoidal com frequência variável, para três modelos matemáticos de sistemas memcapacitivos, é realizada: dado um memcapacitor em série com uma tensão de entrada ac, estuda-se as respectivas funções de histerese carga-tensão por meio de simulação em MATLAB. Em seguida, é realizada uma classificação das curvas de histerese em função da sua geometria, em que a passagem do gráfico no ponto (0,0), de origem dos planos, o define como tipo I ou tipo II. A análise prossegue com a identificação morfológica da área das curvas de histerese obtidas dos primeiro modelo teóricos em causa, variando-se, para isso, amplitude e frequência de entradas, de modo a se comparar os outros dois modelos restantes com este modelo ideal, ao mesmo tempo em que se deseja obter as frequências críticas de cada modelo, ou seja, as frequências e amplitudes a partir das quais a memcapacitância torna-se constante, e o sistema em causa, linear, fazendo então a curva de histerese degenerar para uma reta. A área do primeiro modelo foi calculada através de um algoritmo que calcula a área da curva por meio do Teorema de Green

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

The Effects of Radiation on Memristor-Based Electronic Spiking Neural Networks

In this dissertation, memristor-based spiking neural networks (SNNs) are used to analyze the effect of radiation on the spatio-temporal pattern recognition (STPR) capability of the networks. Two-terminal resistive memory devices (memristors) are used as synapses to manipulate conductivity paths in the network. Spike-timing-dependent plasticity (STDP) learning behavior results in pattern learning and is achieved using biphasic shaped pre- and post-synaptic spikes. A TiO2 based non-linear drift memristor model designed in Verilog-A implements synaptic behavior and is modified to include experimentally observed effects of state-altering, ionizing, and off-state degradation radiation on the device. The impact of neuron “death” (disabled neuron circuits) due to radiation is also examined. In general, radiation interaction events distort the STDP learning curve undesirably, favoring synaptic potentiation. At lower short-term flux, the network is able to recover and relearn the pattern with consistent training, although some pixels may be affected due to stability issues. As the radiation flux and duration increases, it can overwhelm the leaky integrate-and-fire (LIF) post-synaptic neuron circuit, and the network does not learn the pattern. On the other hand, in the absence of the pattern, the radiation effects cumulate, and the system never regains stability. Neuron-death simulation results emphasize the importance of non-participating neurons during the learning process, concluding that non-participating afferents contribute to improving the learning ability of the neural network. Instantaneous neuron death proves to be more detrimental for the network compared to when the afferents die over time thus, retaining the network’s pattern learning capability