Design of Integrated Mixer for 5G Radio Transceiver

The increased demand of high data rate, low latency and wider bandwidth is pushing the wireless communication towards higher frequencies. 3GPP (third generation partnership project) allocated NR (new radio) FR2 (frequency range 2) n257 (26.5 - 29.5 GHz) and n258 (24.25 - 27.5 GHz) bands for high-speed communication. It is challenging to achieve high linearity at higher frequencies with low supply voltage and smaller size devices. This thesis presents design, implementation and simulation results of integrated downconversion mixer for modular 5G radio transceiver. The first stage downconversion mixer, implemented in GF FDSOI 22 nm process will be used in super-heterodyne double downconversion transceiver, operates at 28 GHz input frequency and provides 6-7 GHz intermediate frequency (IF). The pre-layout and post-layout simulation results of double-balanced mixer topologies optimized for high linearity are compared in terms of conversion gain (CG), input third-order intercept point (IIP3), double sideband (DSB) noise figure (NF), LO-to-IF leakage,and dc power consumption. The mixer topologies, including Gilbert cell and variants of Gilbert cell with resistive and inductive degeneration, and mixer with transformer input, show trade-off between conversion gain, linearity, dc power consumption, and area. Under 0.8-V supply voltage, the transformer input mixer achieves highest IIP3 of +16.34 dBm while dc power consumption including LO buffer is 5.7 mW and NFdsb is 13.7 dB

A Study on the Performance Enhancement of the Cascode FET Mixer Using New Common-Source and -Drain Configuration

The wireless communication system has become highly developed of late due to the emergence of various communication technologies, and it is becoming more widely used due to the various information requirements of its users. It has the advantages of mobility and accessibility due to easy information acquisition anytime and anywhere. Thus, the characteristics of low power consumption and high performance are required for the effective power management of the wireless communication system. It depends on a battery for system operation, however, whose efficiency and capacity for highly effective power management is still being investigated. Therefore, as the wireless communication system has limited power, it certainly requires effective RF circuits with low power consumption. The goal of this study is to develop a wireless communication system circuit with enhanced RF performance: the cascode FET mixer with new common-source and -drain circuit configuration. For the high performance of a wireless communication system with low power consumption, a well-designed RF circuit is certainly needed due to its large influence on the performance of the whole wireless communication system. If the mixer circuit is well designed, the whole wireless communication system will exhibit high performance. In this thesis, the enhanced-performance cascode FET mixer using new common-source and -drain circuit configuration is proposed. When the cascode FET mixer using new configuration was compared with the conventional one, it was found that the former has the performance of higher conversion gain at a lower input LO power, a very low noise figure, and very high LO-to-IF isolation. Thus, the proposed cascode FET mixer with enhanced RF performance can improve the performance of the wireless communication system, which can realize effective power consumption because of the use of a local oscillator with lower output power. The cascode FET mixer using new configuration was designed in this study based on the results of the simulation and measurement for the verification of the enhanced RF performance. The results showed the mixer’s enhanced RF performance compared with the conventional cascode FET mixer. The proposed new common-source and -drain circuit configuration in the cascode FET mixer is reported in this thesis for the first time. The cascode FET mixer using new configuration showed effective operation by means of the use of a local oscillator with lower output LO power. It also showed higher conversion gain with only the lower input LO power, which does not need a local oscillator with a large output power as it can be operated at lower input LO power compared with the conventional one. This is the important characteristic for the wireless communication system, which requires effective power consumption. The cascode FET mixer using new configuration showed very high LO-to-IF isolation without a LO rejection filter compared with the conventional one. It showed good LO-to-RF isolation. The cascode FET mixer using new configuration also showed a very low noise figure compared with the conventional one. It uses only a FET, which produces the effect to have very low noise figure due to the thermal and shot noise by an active device. The cascode FET mixer using new configuration showed low output IF power and low linearity for the output IF power of the fundamental and third-order intermodulation frequencies, low than those of the conventional one. It also showed the low output IF power spectrum for the intermodulation distortion of the low-side and up-side bands, as opposed to the conventional one. It showed that each reflection coefficients were about -30 dB for the RF frequency of 2.6 GHz, the LO frequency of 2.5 GHz, and the IF frequency of 100 MHz. Through the aforementioned study results, it is exhibited in this thesis that the proposed cascode FET mixer has enhanced RF performance by means of the new common-source and -drain circuit configuration. It can thus achieve high RF performance without an addition to any other circuit, for the enhancement of the RF performance. Especially, the cascode FET mixer using new configuration showed an indispensable circuit, which it must have to improve the efficiency of the wireless communication system due to the mobility and limited power.Chapter 1. Introduction 1 1.1 Background 2 1.2 Method of study 6 Chapter 2. Fundamental Concepts and Definition of Mixer 7 2.1 Definition of linearity and nonlinearity 8 2.2 Definition of frequency generation 13 2.3 Nonlinear phenomena 19 2.4 Definiton of power and gain 24 2.5 Stability 30 2.6 Mixer performance concept 32 Chapter 3. Cascode FET Mixer Design 46 3.1 Nonlinear FET devices 47 3.2 Conventional cascode FET mixer 57 3.3 Cascode FET mixer using new configuration 64 Chapter 4. Simulation and Measurement Results 76 4.1 Comparison of the simulation results 77 4.2 Comparison of the measurement results 95 Chapter 5. Conclusion 103 References 10

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V

Design of Tunable Low-Noise Amplifier in 0.13um CMOS Technology for Multistandard RF Transceivers

The global market of mobile and wireless communications is witnessing explosive growth in size as well as radical changes. Third generation (3G) wireless systems have recently been deployed and some are still in the process. 3G wireless systems promise integration of voice and data communications with higher data rates and a superior quality of service compared to second generation systems. Unfortunately, more and more communication standards continue to be developed which ultimately requires specific RF/MW and baseband communication integrated circuits that are designed for functionality and compatibility with a specific type of network. Although communication devices such as cellular phones integrate different services such as voice, Bluetooth, GPS, and WLAN, each service requires its own dedicated radio transceiver which results in high power consumption and larger PCB area usage. With the rapid advances in silicon CMOS integrated circuit technology combined with extensive research, a global solutionswhich aims at introducing a global communication system that encompasses all communication standards appears to be emerging. State of the art CMOS technology not only has the capability of operation in the GHz range, but it also provides the advantage of low cost and high level of integration. These features propel CMOS technology as the ideal candidate for current trends, which currently aim to integrate more RF/MW circuits on the same chip. Armed with such technology ideas such as software radio look more attainable than they ever were in the past. Unfortunately, realizing true software radio for mobile applications still remains a tremendous challenge since it requires a high sampling rate and a wide-bandwidth Analog-to-Digital converter which is extremely power hungry and not suitable for battery operated mobile devices. Another approach to realize a flexible and reconfigurable RF/MW transceiver that could operate in a diverse mobile environment and provides a multiband and multistandard solution. The work presented in this thesis focuses on the design of an integrated and tunable low-noise amplifier as part of software defined radio (SDR)

Low-power transceiver design for mobile wireless chemical biological sensors

The design of a smart integrated chemical sensor system that will enhance sensor performance and compatibility to Ad hoc network architecture remains a challenge. This work involves the design of a Transceiver for a mobile chemical sensor. The transceiver design integrates all building blocks on-chip, including a low-noise amplifier with an input-matching network, a Voltage Controlled Oscillator with injection locking, Gilbert cell mixers, and a Class E Power amplifier making it as a single-chip transceiver. This proposed low power 2GHz transceiver has been designed in TSMC 0.35~lm CMOS process using Cadence electronic design automation tools. Post layout HSPICE simulation indicates that Design meets the separation of noise levels by 52dB and 42dB in transmitter and receiver respectively with power consumption of 56 mW and 38 mW in transmit and receive mode

Design of a low-voltage CMOS RF receiver for energy harvesting sensor node

In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology

A 300-800MHz Tunable Filter and Linearized LNA applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.\ud \u

Design of a Phase and Amplitude Detector for a wideband phased array system in SiGe BiCMOS technology

Questo lavoro ha come obiettivo la progettazione di un rilevatore di fase ed ampiezza integrato a banda larga (4-12GHz), da utilizzare come architettura di test on-chip per moduli di trasmissione-ricezione, nell'ambito dei sistemi phased array. Il dispositivo ha la struttura di un direct conversion receiver, e i risultati di simulazione evidenziano la possibilità di effettuare misure accurate con un errore di ampiezza massimo di 0.5dB, ed un errore di fase inferiore a 3°

Design of an Active Harmonic Rejection N-Path Filter for Highly Tunable RF Channel Selection

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve a high-Q band-pass response at high frequencies. The clock frequency determines the center frequency of the band-pass filter, which makes the filter highly tunable over a broad frequency range. Issues with harmonic transfer and poor attenuation limit the feasibility of using N-path filters in practice. The goal of this thesis is to design an integrated active N-path filter that improves upon the passive N-path filter’s poor harmonic rejection and limited outof- band attenuation. The integrated circuit (IC) is implemented using the CMRF8SF 130nm CMOS process. The design uses a multi-phase clock generation circuit to implement a harmonic rejection mixer in order to suppress the 3rd and 5th harmonic. The completed active N-path filter has a tuning range of 200MHz to 1GHz and the out-ofband attenuation exceeds 60dB throughout this range. The frequency response exhibits a 14.7dB gain at the center frequency and a -3dB bandwidth of 6.8MHz