Hardware authentication based on PUFs and SHA-3 2nd round candidates

Security features are getting a growing interest in microelectronics. Not only entities have to authenticate in the context of a high secure communication but also the hardware employed has to be trusted. Silicon Physical Unclonable Functions (PUFs) or Physical Random Functions, which exploits manufacturing process variations in integrated circuits, have been used to authenticate the hardware in which they are included and, based on them, several cryptographic protocols have been reported. This paper describes the hardware implementation of a symmetric-key authentication protocol in which a PUF is one of the relevant blocks. The second relevant block is a SHA-3 2nd round candidate, a Secure Hash Algorithm (in particular Keccak), which has been proposed to replace the SHA-2 functions that have been broken no long time ago. Implementation details are discussed in the case of Xilinx FPGAs.Junta de Andalucía P08-TIC-03674Comunidad Europea FP7-INFSO-ICT-248858Ministerio de Ciencia y Tecnología TEC2008-04920 y DPI2008-0384

Spin quantum computation in silicon nanostructures

Proposed silicon-based quantum-computer architectures have attracted attention because of their promise for scalability and their potential for synergetically utilizing the available resources associated with the existing Si technology infrastructure. Electronic and nuclear spins of shallow donors (e.g. phosphorus) in Si are ideal candidates for qubits in such proposals because of their long spin coherence times due to their limited interactions with their environments. For these spin qubits, shallow donor exchange gates are frequently invoked to perform two-qubit operations. We discuss in this review a particularly important spin decoherence channel, and bandstructure effects on the exchange gate control. Specifically, we review our work on donor electron spin spectral diffusion due to background nuclear spin flip-flops, and how isotopic purification of silicon can significantly enhance the electron spin dephasing time. We then review our calculation of donor electron exchange coupling in the presence of degenerate silicon conduction band valleys. We show that valley interference leads to orders of magnitude variations in electron exchange coupling when donor configurations are changed on an atomic scale. These studies illustrate the substantial potential that donor electron/nuclear spins in silicon have as candidates for qubits and simultaneously the considerable challenges they pose. In particular, our work on spin decoherence through spectral diffusion points to the possible importance of isotopic purification in the fabrication of scalable solid state quantum computer architectures. We also provide a critical comparison between the two main proposed spin-based solid state quantum computer architectures, namely, shallow donor bound states in Si and localized quantum dot states in GaAs.Comment: 14 pages. Review article submitted to Solid State Communication

Control of valley dynamics in silicon quantum dots in the presence of an interface step

Recent experiments on silicon nanostructures have seen breakthroughs toward scalable, long-lived quantum information processing. The valley degree of freedom plays a fundamental role in these devices, and the two lowest-energy electronic states of a silicon quantum dot can form a valley qubit. In this work, we show that a single-atom high step at the silicon/barrier interface induces a strong interaction of the qubit and in-plane electric fields, and analyze the consequences of this enhanced interaction on the dynamics of the qubit. The charge densities of the qubit states are deformed differently by the interface step, allowing non-demolition qubit readout via valley-to-charge conversion. A gate-induced in-plane electric field together with the interface step enables fast control of the valley qubit via electrically driven valley resonance. We calculate single- and two-qubit gate times, as well as relaxation and dephasing times, and present predictions for the parameter range where the gate times can be much shorter than the relaxation time and dephasing is reduced.Comment: 12 pages, 6 figure