137 research outputs found
Neuro-fuzzy chip to handle complex tasks with analog performance
This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of
power consumption, input-output delay and precision performs as a fully analog
implementation. However, it has much larger complexity than its purely analog
counterparts. This combination of performance and complexity is achieved through
the use of a mixed-signal architecture consisting of a programmable analog core of
reduced complexity, and a strategy, and the associated mixed-signal circuitry, to
cover the whole input space through the dynamic programming of this core [1].
Since errors and delays are proportional to the reduced number of fuzzy rules
included in the analog core, they are much smaller than in the case where the whole
rule set is implemented by analog circuitry. Also, the area and the power
consumption of the new architecture are smaller than those of its purely analog
counterparts simply because most rules are implemented through programming.
The Paper presents a set of building blocks associated to this architecture, and gives
results for an exemplary prototype. This prototype, called MFCON, has been
realized in a CMOS 0.7μm standard technology. It has two inputs, implements 64
rules and features 500ns of input to output delay with 16mW of power consumption.
Results from the chip in a control application with a DC motor are also provided
Neuro-fuzzy chip to handle complex tasks with analog performance
This paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input–output delay, and precision, performs as a fully analog implementation.
However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting
of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core.
Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture
are smaller than those of its purely analog counterparts simply because most rules are implemented through programming.
The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype.
This prototype, called multiplexing fuzzy controller (MFCON), has been realized in a CMOS 0.7 um standard technology. It has
two inputs, implements 64 rules, and features 500 ns of input to output delay with 16-mW of power consumption. Results from the chip in a control application with a dc motor are also provided
FPGA implementation of embedded fuzzy controllers for robotic applications
Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/soffivare solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle
FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications
Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle. © 2007 IEEE.Ministerio de Educación y Ciencia TEC2005-04359/MIC y DPI2005-02293Junta de Andalucía TIC2006-635 y TEP2006-37
Controladores difusos adaptativos como módulos de propiedad intelectual para FPGAs
La continua demanda por parte del mercado microelectrónico
de aplicaciones novedosas, con elevados niveles de
complejidad y tiempos de desarrollo cortos ha motivado el
impulso de las técnicas de diseño basadas en el concepto
de “reusabilidad” y el desarrollo de elementos de sistemas
como módulos de propiedad intelectual o módulos IP. En
esta comunicación se describe la implementación de
controladores difusos como módulos IP para FPGAs. Los
controladores operan como periféricos conectables al bus
OPB para los procesadores disponibles en las FPGAs de
Xilinx. El empleo de las memorias internas de las FPGAs
para almacenar las bases de conocimiento permite definir o
ajustar la funcionalidad en tiempo de operación.Ministerio de Educaión y Ciencia TEC2005-04359/MI
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Demonstrating Analog Inference on the BrainScaleS-2 Mobile System
We present the BrainScaleS-2 mobile system as a compact analog inference
engine based on the BrainScaleS-2 ASIC and demonstrate its capabilities at
classifying a medical electrocardiogram dataset. The analog network core of the
ASIC is utilized to perform the multiply-accumulate operations of a
convolutional deep neural network. At a system power consumption of 5.6W, we
measure a total energy consumption of 192uJ for the ASIC and achieve a
classification time of 276us per electrocardiographic patient sample. Patients
with atrial fibrillation are correctly identified with a detection rate of
(93.70.7)% at (14.01.0)% false positives. The system is directly
applicable to edge inference applications due to its small size, power
envelope, and flexible I/O capabilities. It has enabled the BrainScaleS-2 ASIC
to be operated reliably outside a specialized lab setting. In future
applications, the system allows for a combination of conventional machine
learning layers with online learning in spiking neural networks on a single
neuromorphic platform
NeuroBench:Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking
The field of neuromorphic computing holds great promise in terms of advancing computing efficiency and capabilities by following brain-inspired principles. However, the rich diversity of techniques employed in neuromorphic research has resulted in a lack of clear standards for benchmarking, hindering effective evaluation of the advantages and strengths of neuromorphic methods compared to traditional deep-learning-based methods. This paper presents a collaborative effort, bringing together members from academia and the industry, to define benchmarks for neuromorphic computing: NeuroBench. The goals of NeuroBench are to be a collaborative, fair, and representative benchmark suite developed by the community, for the community. In this paper, we discuss the challenges associated with benchmarking neuromorphic solutions, and outline the key features of NeuroBench. We believe that NeuroBench will be a significant step towards defining standards that can unify the goals of neuromorphic computing and drive its technological progress. Please visit neurobench.ai for the latest updates on the benchmark tasks and metrics
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking
The field of neuromorphic computing holds great promise in terms of advancing
computing efficiency and capabilities by following brain-inspired principles.
However, the rich diversity of techniques employed in neuromorphic research has
resulted in a lack of clear standards for benchmarking, hindering effective
evaluation of the advantages and strengths of neuromorphic methods compared to
traditional deep-learning-based methods. This paper presents a collaborative
effort, bringing together members from academia and the industry, to define
benchmarks for neuromorphic computing: NeuroBench. The goals of NeuroBench are
to be a collaborative, fair, and representative benchmark suite developed by
the community, for the community. In this paper, we discuss the challenges
associated with benchmarking neuromorphic solutions, and outline the key
features of NeuroBench. We believe that NeuroBench will be a significant step
towards defining standards that can unify the goals of neuromorphic computing
and drive its technological progress. Please visit neurobench.ai for the latest
updates on the benchmark tasks and metrics
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