Silicon-Based Micromachining Process for Flexible Electronics

In this chapter, we introduce silicon-based micromachining process and devices for flexible electronics application. Silicon-based flexible electronics have the unique advantage over other polymer-based process that leverage the traditional standard CMOS process and can be integrated with scalable IC technology. While integrating with CMOS process, special considerations must be taken into account, such as release process, transfer process, and process integration, in order to produce silicon-based flexible electronics. Several efforts and process developments will be illustrated in this chapter with the highlights of imager and wearable electronics application

Heterogeneous integration of KY(WO4)2-on-glass : a bonding study

Rare-earth ion doped potassium yttrium double tungstate, RE: KY(WO4)(2), is a promising candidate for small, power-efficient, on-chip lasers and amplifiers. There are two major bottlenecks that complicate the realization of such devices. Firstly, the anisotropic thermal expansion coefficient of KY(WO4)(2) makes it challenging to integrate the crystal on glass substrates. Secondly, the crystal layer has to be, for example, < 1 mu m to obtain single mode, high refractive index contrast waveguides operating at 1550 nm. In this work, different adhesives and bonding techniques in combination with several types of glass substrates are investigated. An optimal bonding process will enable further processing towards the manufacturing of integrated active optical KY(WO4)(2) devices. (C) 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreemen

Modeling of CMOS devices and circuits on flexible ultrathin chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)

Vertically integrated modules for low power embedded sensor systems

A typical embedded sensor system consists of an environmental sensor, data storage, and a control circuit (such as a microcontroller). Two main traits desired of these embedded sensor systems are small form factor and low power consumption. However, due to the diverse nature of the design and applications, monolithic solutions incorporating the three main components are often not available on a large cost effective scale. This work describes a method of integrating heterogeneous circuit components into a single module. When combined with efficient operating algorithms the system size is reduced and lifetime is extended. Production or custom designed component chips are thinned and stacked vertically while interconnects are fabricated within the module providing a 3-D integration (3DI) of the system. A Global Positioning System (GPS) location recording sensor system is designed with the intention of applying the 3DI process to reduce its size and power consumption

Ultrathin silicon wafer bonding physics and applications

Ultrathin silicon wafer bonding is an emerging process that simplifies device fabrication, reduces manufacturing costs, increases yield, and allows the realization of novel devices. Ultrathin silicon wafers are between 3 and 200 microns thick with all the same properties of the thicker silicon wafers (greater than 300 microns) normally used by the semiconductor electronics industry. Wafer bonding is one technique by which multiple layers are formed. In this thesis, the history and practice of wafer bonding is described and applied to the manufacture of microelectomechanical systems (MEMS) devices with layer thickness on the scale of microns. Handling and processing problems specific to ultrathin silicon wafers and their bonding are addressed and solved. A model that predicts the conformal nature of these flexible silicon wafers and its impact on bonding is developed in terms of a relatively new description of surface quality, the Power Spectral Density (PSD). A process for reducing surface roughness of silicon is elucidated and a model of this process is described. A method of detecting particle contamination in chemical baths and other processes using wafer bonding is detailed. A final section highlights some recent work that has used ultrathin silicon wafer bonding to fabricate MEMS devices that have reduced existing design complexity and made possible novel, and otherwise difficult to produce, sensors. A new fabrication process that can reduce the required time for proof-of-principle devices using ultrathin silicon wafers is also described

Characterizing stress in ultrathin silicon wafers

The aim of this letter is to calculate the mechanical grinding induced bow and stress in ultrathin silicon wafers. The reverse leakage current of a p-n junction diode fabricated on a 4 in. silicon wafer was measured for wafers thinned to various thicknesses. A correlation with the residual stress was obtained through band gap narrowing effect. The analytical results were compared with experimental bow measurements using a laser profiler. The bow in 50 mu m thick wafer was found to be less than 2 mm using the current grinding process. (c) 2006 American Institute of Physics. (DOI:10.1063/1.2336212

Integration of Bulk Piezoelectric Materials into Microsystems.

Bulk piezoelectric ceramics, compared to deposited piezoelectric thin-films, provide greater electromechanical coupling and charge capacity, which are highly desirable in many MEMS applications. In this thesis, a technology platform is developed for wafer-level integration of bulk piezoelectric substrates on silicon, with a final film thickness of 5-100μm. The characterized processes include reliable low-temperature (200˚C) AuIn diffusion bonding and parylene bonding of bulk-PZT on silicon, wafer-level lapping of bulk-PZT with high-uniformity (±0.5μm), and low-damage micro-machining of PZT films via dicing-saw patterning, laser ablation, and wet-etching. Preservation of ferroelectric and piezoelectric properties is confirmed with hysteresis and piezo-response measurements. The introduced technology offers higher material quality and unique advantages in fabrication flexibility over existing piezoelectric film deposition methods. In order to confirm the preserved bulk properties in the final film, diaphragm and cantilever beam actuators operating in the transverse-mode are designed, fabricated and tested. The diaphragm structure and electrode shapes/sizes are optimized for maximum deflection through finite-element simulations. During tests of fabricated devices, greater than 12μmPP displacement is obtained by actuation of a 1mm2 diaphragm at 111kHz with <7mW power consumption. The close match between test data and simulation results suggests that the piezoelectric properties of bulk-PZT5A are mostly preserved without any necessity of repolarization. Three generations of resonant vibration energy harvesters are designed, simulated and fabricated to demonstrate the competitive performance of the new fabrication process over traditional piezoelectric deposition systems. An unpackaged PZT/Si unimorph harvester with 27mm3 active device volume produces up to 205μW at 1.5g/154Hz. The prototypes have achieved the highest figure-of-merits (normalized-power-density × bandwidth) amongst previously reported inertial energy harvesters. The fabricated energy harvester is utilized to create an autonomous energy generation platform in 0.3cm3 by system-level integration of a 50-80% efficient power management IC, which incorporates a supply-independent bias circuitry, an active diode for low-dropout rectification, a bias-flip system for higher efficiency, and a trickle battery charger. The overall system does not require a pre-charged battery, and has power consumption of <1μW in active-mode (measured) and <5pA in sleep-mode (simulated). Under 1g vibration at 155Hz, a 70mF ultra-capacitor is charged from 0V to 1.85V in 50 minutes.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/1/aktakka_3.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/2/aktakka_2.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/3/aktakka_1.pd

Through Silicon Vias in MEMS packaging, a review

Trough Silicon Via (TSV) is a key enabling technology to achieve the integration of various dies by exploiting the third dimension. This allow the integration of heterogeneous chips in a single package (2.5D integration) or to achieve higher integration densities of transistors (3D integration). These vertical interconnections are widely used for both IC and MEMS devices. This paper reviews TSV technology focusing on their implementation in MEMS sensors with a broad overview on the various fabrication approaches and their constraints in terms of process compatibility. A case study of an inertial MEMS sensor will then be presented.publishedVersio

Thermal dissipation improvement by new technology approach: study, development and characterization

Semiconductor manufacturing requires a silicon substrate to build devices on its front side. The wafer must be thick enough to ensure a stable support during the processing steps. Since the active region of a semiconductor device is limited at the substrate surface, there is a large unused material amount. The material excess causes heat increasing during the operation of the devices. Once the Frond End of Line is completed, the excess material must be removed. Nowadays, there are different thinning techniques adopted in order to reduce the thermal resistance. The thesis project idea is the thermal dissipation improvement with a different approach: instead of reducing the wafer thickness, the adopted technology is exploiting the excess material as a heat sink. The realization of this intrinsic heat sink is achieved by the developing of a suitable process flow, which involves the selective dry etching of the silicon bulk and the subsequent electrodeposition of thick copper. This new process flow offers the advantage of maintaining the wafer “self-support” and allow working with already existing technologies saving on both dedicated thinning technologies and handling technologies. Furthermore, this new approach permits the thermal resistance improvement of semiconductor devices if compared to the standard devices