Low-power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator

We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5V(pp) from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1V(pp) and 1.5V(pp) respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively

4-channel 200 Gb/s WDM O-band silicon photonic transceiver sub-assembly

We demonstrate a 200G capable WDM O-band optical transceiver comprising a 4-element array of Silicon Photonics ring modulators (RM) and Ge photodiodes (PD) co-packaged with a SiGe BiCMOS integrated driver and a SiGe transimpedance amplifier (TIA) chip. A 4 x 50 Gb/s data modulation experiment revealed an average extinction ratio (ER) of 3.17 dB, with the transmitter exhibiting a total energy efficiency of 2 pJ/bit. Data reception has been experimentally validated at 50 Gb/s per lane, achieving an interpolated 10E-12 bit error rate (BER) for an input optical modulation amplitude (OMA) of -9.5 dBm and a power efficiency of 2.2 pJ/bit, yielding a total power efficiency of 4.2 pJ/bit for the transceiver, including heater tuning requirements. This electro-optic subassembly provides the highest aggregate data-rate among O-band RM-based silicon photonic transceiver implementations, highlighting its potential for next generation WDM Ethernet transceivers. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

Four-channel WDM transmitter with heterogeneously integrated III-V/Si photonics and low power 32 nm CMOS drivers

Artículo científicoWe experimentally demonstrate a novel four-channel wavelength division multiplexing transmitter operating at 1.3 μm wavelength employing heterogeneously integrated III-V/Si photonic circuit copackaged with low-power 32-nm SOI CMOS driver integrated circuits (ICs). Error-free operation (BER < 10−12 ) has been achieved across all four channels for back-to-back, 2 and 10 km single-mode fiber transmission at 25 Gb/s per each channel, targeting intra- and inter-datacenter interconnect applications. Power consumption as low as 19.2 mW for four CMOS driver ICs has been recorded, which yields 0.19 pJ/bit energy efficiency

Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

The future of computing beyond Moore's Law.

Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'

Next Generation Silicon Photonic Transceiver: From Device Innovation to System Analysis

Silicon photonics is recognized as a disruptive technology that has the potential to reshape many application areas, for example, data center communication, telecommunications, high-performance computing, and sensing. The key capability that silicon photonics offers is to leverage CMOS-style design, fabrication, and test infrastructure to build compact, energy-efficient, and high-performance integrated photonic systems-on- chip at low cost. As the need to squeeze more data into a given bandwidth and a given footprint increases, silicon photonics becomes more and more promising. This work develops and demonstrates novel devices, methodologies, and architectures to resolve the challenges facing the next-generation silicon photonic transceivers. The first part of this thesis focuses on the topology optimization of passive silicon photonic devices. Specifically, a novel device optimization methodology - particle swarm optimization in conjunction with 3D finite-difference time-domain (FDTD), has been proposed and proven to be an effective way to design a wide range of passive silicon photonic devices. We demonstrate a polarization rotator and a 90◦ optical hybrid for polarization-diversity and phase-diversity communications - two important schemes to increase the communication capacity by increasing the spectral efficiency. The second part of this thesis focuses on the design and characterization of the next- generation silicon photonic transceivers. We demonstrate a polarization-insensitive WDM receiver with an aggregate data rate of 160 Gb/s. This receiver adopts a novel architecture which effectively reduces the polarization-dependent loss. In addition, we demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm in the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is hybridized into the silicon chip by edge-coupling to the silicon chip. The demonstrated packaging method requires only passive alignment and is thus suitable for high-volume production. We also demonstrate all silicon-photonics-based transmission of 34 Gbaud (272 Gb/s) dual-polarization 16-QAM using our integrated laser and silicon photonic coherent transceiver. The results show no additional penalty compared to commercially available narrow linewidth tunable lasers. The last part of this thesis focuses on the chip-scale optical interconnect and presents two different types of reconfigurable memory interconnects for multi-core many-memory computing systems. These reconfigurable interconnects can effectively alleviate the memory access issues, such as non-uniform memory access, and Network-on-Chip (NoC) hot-spots that plague the many-memory computing systems by dynamically directing the available memory bandwidth to the required memory interface

Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

Coherent modulation up to 100 GBd 16QAM using silicon-organic hybrid (SOH) devices

We demonstrate the generation of higher-order modulation formats using silicon-based inphase/quadrature (IQ) modulators at symbol rates of up to 100 GBd. Our devices exploit the advantages of silicon-organic hybrid (SOH) integration, which combines silicon-on-insulator waveguides with highly efficient organic electro-optic (EO) cladding materials to enable small drive voltages and sub-millimeter device lengths. In our experiments, we use an SOH IQ modulator with a {\pi}-voltage of 1.6 V to generate 100 GBd 16QAM signals. This is the first time that the 100 GBd mark is reached with an IQ modulator realized on a semiconductor substrate, leading to a single-polarization line rate of 400 Gbit/s. The peak-to-peak drive voltages amount to 1.5 Vpp, corresponding to an electrical energy dissipation in the modulator of only 25 fJ/bit