Nanophotonic Interconnect Architectures For Many-Core Microprocessors

Nanophotonics is an emerging technology that has the potential to improve the performance and energy consumption of inter- and intra-die communication in future chip multiprocessors. To date, the successful demonstration of a working large-scale system has been hampered by integration challenges and temperature sensitivity of the optical building blocks. Moreover, current approaches to interfacing with these devices are either CMOS incompatible or degrade the potential Tb/s modulation capability to only tens of Gb/s. At first glance it may seem like all of these challenges hint at today's nanophotonic devices being too impractical. However, using a combination of proposed solutions at the device and architectural level, a rich tradeoff space begins to emerge that is still largely untouched due to the knowledge gap between nanophotonic researchers on both sides of the spectrum. To this end, this dissertation attempts to fill this gap by targeting both device and system level research in an integrated fashion. We begin with an extended background and related work section that presents the relevant parameters and functionality of key optical devices for designing interconnection networks at the architecture level. Following this, we give a detailed discussion on the system level implications of optics including communication methods and summaries of recent network architectures for both on-chip and off-chip signaling with important takeaways for designing future systems. The lack of a comprehensive and accurate modeling strategy for optical com- ponents in the architecture community has lead to potentially inaccurate, and inflated, power and performance estimates. Since better representation of optical devices in architectural level simulations is essential to producing trustworthy results, we present a comprehensive, mathematical model for all of the major optical building blocks. To our knowledge, this is the first comprehensive model of all relevant optical devices specifically tailored to system level design for architects. An interesting aspect of architectural research in the field of optics is that there is not a natural progression of scaling parameters that will necessarily dictate future designs as is the case in CMOS. Because nanophotonics is an emerging technology, the potential is limitless for creating new devices that solve previous challenges. Optical packet switching is a promising approach for overcoming the performance and power limitations of bus-based on-chip networks. We present two variations of Phastlane, the first proposed nanophotonic packet switched architecture. In our evaluation, we demonstrate the potential improvements in system performance and power consumption across a range of modulator and receiver parameters. We also augment this analysis with projections for current optical devices using our mathematical device model. Finally, we propose alternatives for overcoming some of the limitations of both Phastlane architectures in the event that future optical components stagnate at current performance and power consumption. Also, we use our device model to explore a less aggressive approach to nanophotonics that judiciously combines electrical and optical interconnect

Architectures and Design Automation for Photonic Networks On Chip

Chip-scale photonics has emerged as an exciting field which can potentially solve many of the problems plaguing the high-performance computing industry, from large-scale to embedded. In theory, photonics is a superior communication medium because of its higher bandwidth density using wave-division multiplexing and bandwidth-power translucency to distance traveled. In practice, physical-layer design and engineering issues such as optical loss, crosstalk, and packaging have slowed its entry into widespread adoption at the chip and board scale. In this work, we present these issues and potential design improvements. The major contributions, however, are the tools and methods we have developed for the design of photonic interconnection networks, including a system-level simulator and CAD and modeling environment for layout, both of which are publicly available to the research community

Energy-efficient electrical and silicon-photonic networks in many core systems

Thesis (Ph.D.)--Boston UniversityDuring the past decade, the very large scale integration (VLSI) community has migrated towards incorporating multiple cores on a single chip to sustain the historic performance improvement in computing systems. As the core count continuously increases, the performance of network-on-chip (NoC), which is responsible for the communication between cores, caches and memory controllers, is increasingly becoming critical for sustaining the performance improvement. In this dissertation, we propose several methods to improve the energy efficiency of both electrical and silicon-photonic NoCs. Firstly, for electrical NoC, we propose a flow control technique, Express Virtual Channel with Taps (EVC-T), to transmit both broadcast and data packets efficiently in a mesh network. A low-latency notification tree network is included to maintain t he order of broadcast packets. The EVC-T technique improves the NoC latency by 24% and the system energy efficiency in terms of energy-delay product (EDP) by 13%. In the near future, the silicon-photonic links are projected to replace the electrical links for global on-chip communication due to their lower data-dependent power and higher bandwidth density, but the high laser power can more than offset these advantages. Therefore, we propose a silicon-photonic multi-bus NoC architecture and a methodology that can reduce the laser power by 49% on average through bandwidth reconfiguration at runtime based on the variations in bandwidth requirements of applications. We also propose a technique to reduce the laser power by dynamically activating/deactivating the 12 cache banks and switching ON/ OFF the corresponding silicon-photonic links in a crossbar NoC. This cache-reconfiguration based technique can save laser power by 23.8% and improves system EDP by 5.52% on average. In addition, we propose a methodology for placing and sharing on-chip laser sources by jointly considering the bandwidth requirements, thermal constraints and physical layout constraints. Our proposed methodology for placing and sharing of on-chip laser sources reduces laser power. In addition to reducing the laser power to improve the energy efficiency of silicon-photonic NoCs, we propose to leverage the large bandwidth provided by silicon-photonic NoC to share computing resources. The global sharing of floating-point units can save system area by 13.75% and system power by 10%

Hybrid Router Design for High Performance Photonic Network-On-Chip

With rising density of cores in Chip-Multiprocessors, traditional metallic interconnects won't be able to cater to the high demand in communication bandwidth at lower power consumption. Photonic interconnects are emerging as a very competitive and promising alternative to address these bottlenecks in recent times. The infrastructure for realizing such a communication architecture comprises of Micro Ring-resonator based silicon nano-photonic routers and waveguides. We propose a novel 5x5 photonic router microarchitecture employing mode-division-multiplexing along with wavelength-division-multiplexing and time-division-multiplexing. It increases the aggregate bandwidth almost four times in a network consuming almost 30% less power as compared to other recent photonic routers and laying the foundation of a high performance photonic network-on-chip(PNoC). We validated the feasibility of the proposed architecture and developed a new circuit switched based network simulator(PhotoNoxim) based on the router microarchitecture proposed by us to validate it under various synthetic traffics and benchmark applications

Subchannel Scheduling for Shared Optical On-chip Buses

Maximizing bandwidth utilization of optical on-chip interconnects in essential to compensate for static power overheads in optical networks-on-chip. Shared optical buses were shown to be a power-efficient, modular design solution with tremendous power saving potential by allowing optical bandwidth to be shared by all connected nodes. Previous proposals resolve bus contention by scheduling senders sequentially on the entire optical bandwidth; however, logically splitting a bus into sub-channels to allow both sequential and parallel data transmission has been shown to be highly efficient in electrical interconnects and could also be applied to shared optical buses. In this paper, we propose an efficient subchannel scheduling algorithm that aims to minimize the number of bus utilization cycles by assigning sender-receiver pairs both to subchannels and time slots. We present both a distributed and a centralized bus arbitration scheme and show that both can be implemented with low overheads. Our results show that subchannel scheduling can more than double throughput on shared optical buses compared to sequential scheduling without any power overheads in most cases. Arbitration latency overheads compared to state-of-the-art sequential schemes are moderate-to-low for significant bus bandwidths and only noticeable for low injection rates

Architectural Exploration and Design Methodologies of Photonic Interconnection Networks

Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on- and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this work, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks. We examine several photonic networks through the synergistic study of both physical-layer metrics and system-level metrics. This holistic analysis method enables us to provide deeper insight into architecture scalability since it considers insertion loss, crosstalk, and power dissipation. In addition to these novel physical-layer metrics, traditional system-level metrics of bandwidth and latency are also obtained. Lastly, we propose a novel routing architecture known as wavelength-selective spatial routing. This routing architecture is analogous to electronic virtual channels since it enables the transmission of multiple logical optical channels through a single physical plane (i.e. the waveguides). The available wavelength channels are partitioned into separate groups, and each group is routed independently in the network. Each partition is spectrally multiplexed, as opposed to temporally multiplexed in the electronic case. The wavelength-selective spatial routing technique benefits network designers by provider lower contention and increased path diversity