Space Radiation and Impact on Instrumentation Technologies

Understanding the interactions of the Sun, Earth and other natural and man-made objects in the solar system with the space radiation environment is crucial for improving activities of humans on Earth and in space. An important component of understanding these interactions is their effects on the instrumentation required in the exploration of air and space. NASA's Glenn Research Center (GRC) fills the role of developing supporting technologies to enable improved instruments for space science missions, as well as improved instruments for aeronautics and ground-based applications. In this review, the space radiation environment and its effects are outlined, as well the impact it has on instrumentation and the technology that GRC is developing to improve performance for space science

The Study of Optical and Electrical Properties of Nanostructured Silicon Carbide Thin Films Grown by Pulsed-Laser Deposition

In this paper, nanostructured silicon carbide (SiC) thin films are deposited onto glass substrate using pulsed laser deposition technique. Electrical and optical characterizations such as conductivity, resistivity, transmission, Seeback effect, absorption, absorption coefficient, energy band gap, and extinction coefficient as a function of photon energy, and the effect of thin films thickness on transmission are carried out to characterize the prepared samples. Results showed that the prepared SiC thin film is an n-type semiconductor with an indirect bandgap of ~3 eV, 448 nm cutoff wavelength, 3.4395 × 104 cm−1 absorption coefficient and 0.154 extinction coefficient. The surface morphology of the SiC thin films is studied using scanning electron microscope at a substrate temperature of 400 °C and it is found that the grain size of the prepared SiC thin film is about 30 nm. As such, the nano thin films optical and structural characteristics enable the films to be used as gases sensors in many optoelectronic devices such as the environment and ultraviolet photodiode

Introduction to Graphene Electronics -- A New Era of Digital Transistors and Devices

The speed of silicon-based transistors has reached an impasse in the recent decade, primarily due to scaling techniques and the short-channel effect. Conversely, graphene (a revolutionary new material possessing an atomic thickness) has been shown to exhibit a promising value for electrical conductivity. Graphene would thus appear to alleviate some of the drawbacks associated with silicon-based transistors. It is for this reason why such a material is considered one of the most prominent candidates to replace silicon within nano-scale transistors. The major crux here, is that graphene is intrinsically gapless, and yet, transistors require a band-gap pertaining to a well-defined ON/OFF logical state. Therefore, exactly as to how one would create this band-gap in graphene allotropes is an intensive area of growing research. Existing methods include nano-ribbons, bilayer and multi-layer structures, carbon nanotubes, as well as the usage of the graphene substrates. Graphene transistors can generally be classified according to two working principles. The first is that a single graphene layer, nanoribbon or carbon nanotube can act as a transistor channel, with current being transported along the horizontal axis. The second mechanism is regarded as tunneling, whether this be band-to-band on a single graphene layer, or vertically between adjacent graphene layers. The high-frequency graphene amplifier is another talking point in recent research, since it does not require a clear ON/OFF state, as with logical electronics. This paper reviews both the physical properties and manufacturing methodologies of graphene, as well as graphene-based electronic devices, transistors, and high-frequency amplifiers from past to present studies. Finally, we provide possible perspectives with regards to future developments.Comment: This is an updated version of our review article, due to be published in Contemporary Physics (Sept 2013). Included are updated references, along with a few minor corrections. (45 pages, 19 figures

Single pulse avalanche robustness and repetitive stress ageing of SiC power MOSFETs

This paper presents an extensive electro-thermal characterisation of latest generation silicon carbide (SiC) Power MOSFETs under unclamped inductive switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their aging under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development

The Conference on High Temperature Electronics

The status of and directions for high temperature electronics research and development were evaluated. Major objectives were to (1) identify common user needs; (2) put into perspective the directions for future work; and (3) address the problem of bringing to practical fruition the results of these efforts. More than half of the presentations dealt with materials and devices, rather than circuits and systems. Conference session titles and an example of a paper presented in each session are (1) User requirements: High temperature electronics applications in space explorations; (2) Devices: Passive components for high temperature operation; (3) Circuits and systems: Process characteristics and design methods for a 300 degree QUAD or AMP; and (4) Packaging: Presently available energy supply for high temperature environment

A comprehensive study on the avalanche breakdown robustness of silicon carbide power MOSFETs

This paper presents an in-depth investigation into the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs comprising of functional as well as structural characterization and the corresponding underlying physical mechanisms responsible for device failure. One aspect of robustness for power MOSFETs is determined by its ability to withstand energy during avalanche breakdown. Avalanche energy (EAV) is an important figure of merit for all applications requiring load dumping and/or to benefit from snubber-less converter design. 2D TCAD electro-thermal simulations were performed to get important insight into the failure mechanism of SiC power MOSFETs during avalanche breakdow

Performance benchmark of Si IGBTs vs. SiC MOSFETs in small-scale wind energy conversion systems

Modern power electronics devices based on SiC power MOSFETs technology become more demanding in the last few years. They show better performance over Si-IGBTs on renewable energy power conversion systems due to their higher switching frequency, higher temperature capability, higher power density and higher reliability. This paper presents a benchmarking of SiC-MOSFET and Si-IGBT power devices with the voltage rating of 1200V in 2-Level Full-Bridge (2L-FB) inverter for 10kW small scale wind turbine. By simulation, the inverter performance is evaluated in the presence of the wind speed distribution profile and the reference switching frequency value for SiC devices in this topology at this power level is determined. The results show that the SiC solution can improve the efficiency, save energy and reduce the size and cost due to high switching frequency and temperature capabilities

Non-Micropipe Dislocations in 4H-SiC Devices: Electrical Properties and Device Technology Implications

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vectors greater than or equal to 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = 1c with no hollow core) in densities on the order of thousands per sq cm, nearly 100-fold micropipe densities. While not nearly as detrimental to SiC device performance as micropipes, it has recently been demonstrated that elementary screw dislocations somewhat degrade the reverse leakage and breakdown properties of 4H-SiC p(+)n diodes. Diodes containing elementary screw dislocations exhibited a 5% to 35% reduction in breakdown voltage, higher pre-breakdown reverse leakage current, softer reverse breakdown I-V knee, and microplasmic breakdown current filaments that were non-catastrophic as measured under high series resistance biasing. This paper details continuing experimental and theoretical investigations into the electrical properties of 4H-SiC elementary screw dislocations. The nonuniform breakdown behavior of 4H-SiC p'n junctions containing elementary screw dislocations exhibits interesting physical parallels with nonuniform breakdown phenomena previously observed in other semiconductor materials. Based upon experimentally observed dislocation-assisted breakdown, a re-assessment of well-known physical models relating power device reliability to junction breakdown has been undertaken for 4H-SiC. The potential impact of these elementary screw dislocation defects on the performance and reliability of various 4H-SiC device technologies being developed for high-power applications will be discussed

Advanced CMOS Process for Submicron Silicon Carbide (SiC) Device

Silicon carbide (SiC) is a wide semiconductor material with superior material properties compared to other rival materials. Due to its fewer dislocation defects than gallium nitride and its ability to form native oxides, this material possesses an advantage among wide band gap materials. Despite having several superior properties its low voltage application is less explored. CMOS is extremely important in low voltage areas and silicon is the dominant player in it for the last 50 years where scaling has contributed a major role in this flourishment. The channel length of silicon devices has reached 3 nm whereas SiC is still in the micrometer (2 μm/ 1.2 μm) range. So, SiC technology is still in its infancy which can be compared with silicon technology in the mid-1980s range. When the SiC devices would enter into the sub-micron and deep submicron range, proper device design in those ranges is necessary to rip the benefit of scaling. In this thesis, the SiC CMOS process available from different institutes and foundries is discussed first to understand the current state of the art. Later, low-voltage conventional SiC NMOS devices in the submicron range (2 μm to 600 nm) are simulated and their key parameters and performances are analyzed. In the submicron range, one major issue in MOSFET scaling is hot carrier effects. Thus to minimize this effect, a low-doped drain (LDD) region is introduced in the conventional SiC design having a channel length of 800 nm and 600 nm. In comparison with conventional designs, LDD designs have shown better saturation current behavior, reduced threshold roll-off, reduced hot electron current density, minimized gate leakage, reduced body hole current, enhanced voltage handling capability, reduced electric field, and improved subthreshold behavior in SiC. In the end, spacer technology, dopants, doping methods, and LDD realization technique in SiC are discussed