Vertical III-V Nanowire Transistors for Low-Power Electronics

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V

Compact Modeling of Intrinsic Capacitances in Double-Gate Tunnel-FETs

La miniaturització dels MOSFET en els circuits integrats ha elevat la tecnologia microelectrònica. Aquesta tendència també augmenta el grau de complexitat d'aquests circuits i els seus components bàsics. En els MOSFET convencionals, el corrent es basa en l'emissió termoiònica de portadors de càrrega, que per això limita el pendent subumbral en aquests transistors a 60 mV / dec. Per tant, per superar aquest límit i continuar amb la miniaturització per mantenir el ritme de la llei de Moore, es requereixen estructures alternatives. Entre aquestes, el transistor d'efecte de camp per túnel (TFET) es considera un possible successor de l'MOSFET. A causa del seu mecanisme alternatiu de transport de corrent, conegut com a túnel de banda a banda (B2B), el pendent subumbral en TFET pot fer-se inferior al límit de 60 mV / dec. Per comprendre i estimar el comportament dels TFET, no només com un element únic sinó també a nivell de circuit, es requereix un model compacte d'aquest dispositiu. En aquesta tesi es presenta un model basat en càrrega per descriure el comportament capacitiu d'un TFET de doble porta (DG TFET). No obstant això, la simplicitat i la flexibilitat de el model permeten usar-lo per a un altre tipus d'estructures TFET, com els TFET planars o de nanofils d'una sola porta (SG TFETs). El model és verificat amb les simulacions TCAD, així com amb mesures experimentals de TFET fabricats. El model de capacitància també inclou l'efecte dels elements paràsits. A més, en el context d'aquest treball també s'investiga la influència dels contactes de barrera Schottky en el comportament capacitiu dels TFET. Aquest model finalment es combina amb un model DC compacte existent per formar un model TFET compacte complet. A continuació, el model compacte s'implementa per a simulacions transitòries de circuits oscil·ladors d'anell basats en TFET.La miniaturización de los MOSFET en los circuitos integrados ha elevado la tecnología microelectrónica. Esta tendencia también aumenta el grado de complejidad de estos circuitos y sus componentes básicos. En los MOSFET convencionales, la corriente se basa en la emisión termoiónica de portadores de carga, que por ello limita la pendiente subumbral en estos transistores a 60 mV/dec. Por tanto, para superar este límite y continuar con la miniaturización para mantener el ritmo de la ley de Moore, se requieren estructuras alternativas. Entre estas, el transistor de efecto de campo por túnel (TFET) se considera un posible sucesor del MOSFET. Debido a su mecanismo alternativo de transporte de corriente, conocido como túnel de banda a banda (B2B), la pendiente subumbral en TFET puede hacerse inferior al límite de 60 mV/dec. Para comprender y estimar el comportamiento de los TFET, no sólo como un elemento único sino también a nivel de circuito, se requiere un modelo compacto de este dispositivo. En esta tesis se presenta un modelo basado en carga para describir el comportamiento capacitivo de un TFET de doble puerta (DG TFET). Sin embargo, la simplicidad y la flexibilidad del modelo permiten usarlo para otro tipo de estructuras TFET, como los TFET planares o de nanohílos de una sola puerta (SG TFETs). El modelo es verificado con las simulaciones TCAD, así como con medidas experimentales de TFET fabricados. El modelo de capacitancia también incluye el efecto de los elementos parásitos. Además, en el contexto de este trabajo también se investiga la influencia de los contactos de barrera Schottky en el comportamiento capacitivo de los TFET. Este modelo finalmente se combina con un modelo DC compacto existente para formar un modelo TFET compacto completo. A continuación, el modelo compacto se implementa para simulaciones transitorias de circuitos osciladores de anillo basados en TFET.Miniaturization of the MOSFETs on the integrated circuits has elevated the microelectronic technology. This trend also increases the degree of complexity of these circuits and their building blocks. In conventional MOSFETs the current is based on the thermionic—emission of charge carrier, which therefore limits the subthreshold swing in these transistors to 60 mV/dec. Hence, to overcome this limit and continue with down scaling to keep pace with the Moor’s law, alternative structures are required. Among these, the tunnel—field—effect transistor (TFET) is considered as a potential successor of the MOSFET. Due to its alternative current transport mechanism, known as band—to—band (B2B) tunneling, the subthreshold swing in TFETs can overcome the 60 mV/dec limit. In order to comprehend and estimate the behavior of TFETs, not only as a single element but also on the circuit level, a compact model of this device is required. In this dissertation a charge –based model to describes the capacitive behavior of a double—gate (DG) TFET is presented. However, simplicity and flexibility of the model allow to use it for other type of TFET structures such as single—gate (SG) planar or nanowire TFETs. The model is verified with the TCAD simulations as well as the measurement data of fabricated TFETs. The capacitance model also includes the effect of the parasitic elements. Furthermore, in the context of this work also the influence of Schottky barrier contacts on the capacitive behavior of TFETs is investigated. This model is finally combined with an existing compact DC model to form a complete compact TFET model. The compact model is then implemented for transient simulations of TFET—based inverter and ring—oscillator circuits

A review of selected topics in physics based modeling for tunnel field-effect transistors

The research field on tunnel-FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band-to-band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non-self-consistent quantum models, where BTBT is computed with rigorous quantum-mechanical models starting from frozen potential profiles and closed-boundary Schr\uf6dinger equation problems. We will then address models that solve the open-boundary Schr\uf6dinger equation problem, based either on the non-equilibrium Green's function NEGF or on the quantum-transmitting-boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero-structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field

Modeling and Fabrication of Low Power Devices and Circuits Using Low-Dimensional Materials

University of Minnesota Ph.D. dissertation.July 2016. Major: Electrical Engineering. Advisor: Steven Koester. 1 computer file (PDF); x, 112 pages.As silicon approaches its ultimate scaling limit as a channel material for conventional semiconductor devices, alternate mechanisms and materials are emerging rapidly to replace or complement conventional silicon based devices. Attractive semiconducting properties such as high mobility, excellent interface quality, and better scalability are the properties desired for materials to be explored for electronic and photonic device applications. Hybrid III-V semiconductor based tunneling field effect transistors (TFETs) can provide a strong alternative due to their attractive properties such as subthreshold slopes less than 60 mV/decade, which can lead to aggressive power supply scaling. Here, InAs-SiGe-Si based TFETs are studied in detail. Simulations predict that subthreshold slopes as low as 18 mV/decade and on currents as high as 50 µA/µm can be achieved using such a device. However, the simulations also show that the device performance is limited by (1) the low density of states in the source which induces a trade-off between the source doping and the subthreshold slope, limiting power supply scaling, and (2) direct source-to-drain tunneling which limits gate length scaling. Another approach to explore low power alternatives to conventional semiconductor device can be to use emerging two-dimensional (2D) materials. In particular, the transition metal dichalcogenides (TMDs) are promising material group that, like graphene, these material exhibit 2D nature, but unlike graphene, have a finite band gap. In this work, the off-state characteristics are modelled for MoS2 MOSFETs (metal–oxide–semiconductor field-effect transistors), and their circuit performance is predicted. MoS2 Due to its higher effective masses and large band gap compared to silicon it is shown that MoS2 MOSFETs are well suited for dynamic memory applications. Two of such circuits, one transistor one capacitor (1TIC) and two transistor (2T) dynamic memory cells have been fabricated for the first time. Retention times as high as 0.25 second and 1.3 second for the 1T1C and 2T cell, respectively, are demonstrated. Moreover, ultra-low leakage currents less than femto-ampere per micron are extracted based on the retention time measurements. These results establish the potential of 2D MoS2 as an attractive material for low power device and circuit applications

Modeling and optimization of Tunnel-FET architectures exploiting carrier gas dimensionality

The semiconductor industry, governed by the Moore's law, has achieved the almost unbelievable feat of exponentially increasing performance while lowering the costs for years. The main enabler for this achievement has been the scaling of the CMOS transistor that allowed the manufacturers to pack more and more functionality into the same chip area. However, it is now widely agreed that the happy days of scaling are well over and we are about to reach the physical limits of the CMOS concept. One major, insurmountable limit of CMOS is the so-called thermionic emission limit which dictates that the switching slope of the transistor cannot go below 60mV/dec at room temperature. This makes it impossible to scale down the supply voltage for CMOS transistor without dramatically increasing the static power consumption. To address this issue, a novel transistor concept called Tunnel FET (TFET) which utilizes the quantum mechanical band-to-band tunneling (BTBT) has been proposed. TFETs possess the potential to overcome the thermionic emission limit and therefore allow for low supply voltage operation. This thesis aims at investigating the performance of TFETs with alternative architectures exploiting quantized carrier gases through quantum mechanical simulations. To this end, 1D and 2D self-consistent Schrödinger-Poisson solvers with closed boundaries are developed along with the phonon-assisted and direct BTBT models implemented as a post-processing step. Moreover, we propose an efficient method to incorporate the quantization along the transverse direction which enables us to simulate different dimensionality combinations. The implemented models are calibrated against experimental and more fundamental quantum mechanical simulation methods such as k.p and tight-binding NEGF using tunneling diode structures. Using these tools, we simulate an advanced TFET architecture called electron-hole bilayer TFET (EHBTFET) which exploits BTBT between 2D electron and hole gases electrostatically induced by two separate oppositely biased gates. The subband-to-subband tunneling is first analyzed with the 1D simulator where the device working principle is demonstrated. Then, non-idealities of the EHBTFET operation such as the lateral tunneling and corner effects are investigated using the 2D simulator. The origin of the lateral leakage and techniques to reduce it are analyzed in detail. A parameter space analysis of the EHBTFET is performed by simulating a wide range of channel materials, channel thickness and oxide thicknesses. Our results indicate the possibility of having 2D-2D and 3D-3D tunneling for the EHBTFET, depending on the parameters chosen. A novel digital logic scheme utilizing the independent biasing property of the EHBTFET n- and p-gates is proposed and verified through quantum-corrected TCAD simulations. The performance benchmarking against a 28nm FD-SOI CMOS technology is performed as well. The results indicate that the EHBTFET logic can outperform the CMOS counterpart in the low supply voltage (subthreshold) regime, where it can offer significantly higher drive current due to its steep switching slope. We also compare the different dimensionality cases and highlight important differences between the face and edge tunneling devices in terms of their dependence on the device parameters (channel material, channel thickness and EOT)

Improving the Performance of Nanoscale Field-Effect Transistors Through Electrostatic Engineering

The continued scaling of field-effect transistors (FETs) requires that nearly every aspect of these devices be optimized to ensure that they can continue to meet practical performance requirements. However, scaling the channel lengths of FETs naturally enhances electrostatic and quantum mechanical short-channel effects, thereby increasing leakage currents in the OFF-state, reducing driving currents in the ON-state, and making it difficult for FETs attain optimal switching behaviours. To mitigate these detrimental effects, it is imperative to (i) thoroughly understand the electrostatic operation of nanoscale FETs and (ii) establish novel design strategies to mitigate short-channel effects. In this thesis, I address these two challenges by studying the electrostatic operation of nanoscale FETs using simulation techniques. In particular, I use the non-equilibrium Green's function method, an atomistic quantum transport simulation technique, to study the electrostatic operation of MOSFETs and to assess the utility of novel electrostatic design strategies for nanoscale FETs. The body of this thesis is divided into three main works. In the first, I study how individual elements of a metal-oxide-semiconductor FET's (MOSFET's) semiconductor's anisotropic permittivity affect device performance, and I establish electrostatic-based guidelines for selecting optimal semiconductors for future MOSFETs. Next, I study how replacing an FET's conventional isotropic insulators (i.e. gate insulator and spacers) with anisotropic insulators can improve the performance of both conventional MOSFETs and tunnel FETs, and I propose novel insulator architectures to further optimize the performance of these devices. Finally, in my third study, I examine how fringe-induced barrier lowering, an electrostatic short-channel effect created by implementing high-κ gate insulators, can be exploited to suppress quantum mechanical short-channel effects (source-to-drain tunneling) to improve the overall performance of nanoscale MOSFETs. The operating principles and design rules established in these three works extend the current picture of the electrostatic operation and design rules for nanoscale FETs to help device designers continue to scale FETs while meeting essential performance benchmarks

Technological Solution beyond MOSFET and Binary Logic Device

Title from PDF of title page viewed January 31, 2019Thesis advisor: Masud ChowdhuryVitaIncludes bibliographical references (pages 64-70)Thesis (M.S.)--School of Computing and Engineering, University of Missouri--Kansas City, 2018Today’s technology is based on the binary number system-based circuitry, which is the outcome of the simple on and off switching mechanism of the prevailing transistors. Consideration of higher radix number system can eradicate or lessen many limitations of binary number system such as the saturation of Moore’s law. The most substantial potential benefits of higher radix approaches are the decrease of wiring complexity. Excessive scaling of the technologies has led the researchers beyond Binary Logic and MOSFET technology. TFET considered as one of the most promising options for low-power application for beyond MOSFET technologies. Graphene Nano Ribbon, due to its high-carrier mobility, tunable bandgap and its outstanding electrostatic control of device gate becomes ideal choice for channel material of TFET. This paper proposes double gated ultra-thin body (UTB) TFET device model using Graphene nano ribbon as the channel material. In this paper evaluation of the model by performing the comparative analysis with InAs as the channel material in terms of Ec-Ev on and off state and Id-Vg characteristics is presented. The feasibility of multi valued logic system in real-world rests on two serious aspects, such as, the easiness of mathematical approach for implementing the multivalued logic into today’s technology and the sufficiency of synthesis techniques. In this paper, we have focused on the different technology available for implementing multivalued logic especially ternary logic. Ternary logic devices are expected to lead to an exponential increase of the information handling capability, which binary logic cannot support. Memory capacitor or memcapacitor is an emerging device that exhibits hysteresis behavior, which can be manipulated by external parameters, such as, the applied electric field or voltage. One of the unique properties of the memcapacitor is that by using the percolation approach, we can achieve Metal-Insulator-Transition (MIT) phenomenon, which can be utilized to obtain a staggered hysteresis loop. For multivalued logic devices staggered hysteresis behavior is the critical requirement. In this paper, we propose a new conceptual design of a ternary logic device by vertically stacking dielectric material interleaved with layers of graphene nanoribbon (GNR) between two external metal plates. The proposed device structure displays the memcapacitive behavior with the fast switching metal-to-insulator transition in picosecond scale. The device model is later extended into a vertical-cascaded version, which acts as a ternary device.Introduction -- Multi valued logic -- Overview of different MVL technologies -- Graphene memcapacitor based ternary logic device -- Graphene nano ribbon based TFET -- Conclusion and future wor

Two-Dimensional Electronic Materials and Devices: Opportunities and Challenges

The unprecedented growth of the Internet of Things (IoT) and the 4th Industrial Revolution (Industry 4.0) not only demands dimensional scaling of device technologies but also new types of applications beyond today’s electronics. Two-dimensional (2D) materials, a group of layered crystals (such as graphene and MoS2) with unique properties, have emerged as promising candidates for IoT and Industry 4.0 since they can, not only extend the scaling with unprecedented performance and energy efficiency but also exhibit high potential for novel electronic devices. However, such nanomaterials suffer from significant challenges in process integration, especially in the modules that involves the formation of interfaces between 2D materials and conventional bulk materials. Thus, realizing high-performance energy-efficient 2D electronic devices has been challenging. This dissertation focuses on understanding the fundamental issues in such 2D materials (such as contacts, interfaces and doping) and in identifying applications uniquely enabled by these materials.First, a comprehensive treatment of metal contacts to 2D semiconductors, which has been a huge hurdle for 2D electronic technologies, will be presented. As a pioneering study, new interface physics originating from the unique dimensionality and surface properties have been revealed [1]. Solutions to minimize contact resistance are described though techniques of interface hybridization [2] and seamless contacts [3], [4]. These techniques transform 2D semiconductors from solely scientifically-interesting materials into high-performance field-effect transistor (FET) technologies, such as MoS2 FETs with record-low contact resistances [5], [6] and WSe2 FETs with record-high drive current and mobility [7]. Beyond metal interfaces, dielectric interface is crucial for preserving the carrier mobility in 2D channels, for which a solution enabled by buffer layers has been proposed [8]. On the other hand, the vertical van der Waals interfaces between 2D and 3D semiconductors, which retain the advantages of pristine ultra-thin 2D films as well as maximized tunneling area/field, have been studied and exploited into a novel beyond-silicon transistor technology – the first 2D channel tunnel FET (TFET) [9], which beat the fundamental limitation in the switching behavior of transistors. Recent results from the engineering of such 2D-3D semiconductor interfaces by surface reduction/passivation are described, showing a significant boost of drive current. While conventional diffusion/ion implantation methods are infeasible for 2D materials, two efficient doping techniques that are specific for 2D materials – surface doping [10], [11] and intercalation doping [12] are presented. The theoretical study of surface doping using ab-initio methods helped develop a novel doping scheme that uniquely exploits the Lewis-base like pedigree of 2D semiconductors without disturbing the structural integrity of the 2D atomic layer configuration [13], as well as a novel electrocatalyst based on MoS2 that achieved record high hydrogen evolution reaction (HER) performance [14]. On the other hand, intercalation doping has been employed to demonstrate graphene based transparent electrodes with the best combination of transmittance and sheet resistance [12], and also the first graphene interconnects with excellent performance, reliability and energy-efficiency [15], [16]. Moreover, by uniquely exploiting the high kinetic inductance and conductivity of intercalation doped graphene, a fundamentally different on-chip inductor has been demonstrated [17], [18], with both small form-factors and high inductance values, that were once thought unachievable in tandem. This 2D technique provides an attractive solution to the longstanding scaling problem of analog/radio-frequency electronics and opens up an unconventional pathway for the development of future ultra-compact wireless communication systems. Finally, a novel dissipative quantum transport methodology based on Büttiker probes with band-to-band tunneling capability is developed for 2D FETs [19]. Subsequently, gate-induced-drain-leakage (GIDL), one of the main leakage mechanisms in FETs especially access transistors, is evaluated for the first time for 2D FETs. The results establish the advantages of certain 2D semiconductors in greatly reducing GIDL and thereby support use of such materials in future memory technologies.The dissertation concludes with a vision for how a smart life can be realized in the future by harnessing the capabilities of various 2D technologies in the era of IoT and Industry 4.0.[1] J. Kang, D. Sarkar, W. Liu, D. Jena, and K. Banerjee, “A computational study of metal-contacts to beyond-graphene 2D semiconductor materials,” in IEEE International Electron Devices Meeting, 2012, pp. 407–410.[2] J. Kang, W. Liu, D. Sarkar, D. Jena, and K. Banerjee, “Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors,” Phys. Rev. X, vol. 4, no. 3, p. 31005, Jul. 2014.[3] J. Kang, D. Sarkar, Y. Khatami, and K. Banerjee, “Proposal for all-graphene monolithic logic circuits,” Appl. Phys. Lett., vol. 103, no. 8, p. 83113, 2013.[4] A. Allain, J. Kang, K. Banerjee, and A. Kis, “Electrical contacts to two-dimensional semiconductors,” Nat. Mater., vol. 14, no. 12, pp. 1195–1205, 2015.[5] W. Liu et al., “High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance,” in IEEE International Electron Devices Meeting, 2013, pp. 499–502.[6] J. Kang, W. Liu, and K. Banerjee, “High-performance MoS2 transistors with low-resistance molybdenum contacts,” Appl. Phys. Lett., vol. 104, no. 9, p. 93106, Mar. 2014.[7] W. Liu, J. Kang, D. Sarkar, Y. Khatami, D. Jena, and K. Banerjee, “Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors.,” Nano Lett., vol. 13, no. 5, pp. 1983–90, May 2013.[8] J. Kang, W. Liu, and K. Banerjee, “Computational Study of Interfaces between 2D MoS2 and Surroundings,” in 45th IEEE Semiconductor Interface Specialists Conference, 2014.[9] D. Sarkar et al., “A subthermionic tunnel field-effect transistor with an atomically thin channel,” Nature, vol. 526, no. 7571, pp. 91–95, Sep. 2015.[10] Y. Khatami, W. Liu, J. Kang, and K. Banerjee, “Prospects of graphene electrodes in photovoltaics,” in Proceedings of SPIE, 2013, vol. 8824, p. 88240T–88240T–6.[11] D. Sarkar et al., “Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing,” Nano Lett., vol. 15, no. 5, pp. 2852–2862, May 2015.[12] W. Liu, J. Kang, and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene,” IEEE Electron Device Lett., vol. 37, no. 9, pp. 1246–1249, Sep. 2016.[13] S. Lei et al., “Surface functionalization of two-dimensional metal chalcogenides by Lewis acid–base chemistry,” Nat. Nanotechnol., vol. 11, no. 5, pp. 465–471, Feb. 2016.[14] J. Li, J. Kang, Q. Cai, W. Hong, C. Jian, and W. Liu, “Boosting Hydrogen Evolution Performance of MoS2 by Band Structure Engineering,” Adv. Mater. Interfaces, vol. 1700303, 2017.[15] J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects,” Nano Lett., vol. 17, no. 3, pp. 1482–1488, Mar. 2017.[16] J. Jiang, J. Kang, and K. Banerjee, “Characterization of Self - Heating and Current - Carrying Capacity of Intercalation Doped Graphene - Nanoribbon Interconnects,” in IEEE International Reliability Physics Symposium, 2017, p. 6B.1.1-6B.1.6.[17] X. Li et al., “Graphene inductors for high-frequency applications - design, fabrication, characterization, and study of skin effect,” in IEEE International Electron Devices Meeting, 2014, p. 5.4.1-5.4.4.[18] J. Kang et al., under review.[19] J. Kang et al., under review

Advanced Transistors for Supply Voltage Reduction: Tunneling Field-Effect Transistors and High-Mobility MOSFETS

Ph.DDOCTOR OF PHILOSOPH