11 research outputs found
Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File
Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future technology generations. NBTI Aging of a Static Random Access Memory (SRAM) cell leads to a lower noise margin, thereby increasing the failure rate. The register file, which consists of an array of SRAM cells, can suffer from data loss, leading to a system failure. In this work, we study the source of NBTI stress in an architecture and physical register file. Based on our study, we modified the register file structure to reduce the NBTI degradation and improve the overall system reliability. Having evaluated new register file structures, we find that our techniques substantially improve reliability of the register files. The new register files have small overhead, while in some cases they provide saving in area and power
Robust Design of Variation-Sensitive Digital Circuits
The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to
12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors
(ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more
difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the
devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process
variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric
yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random
Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower
power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that
the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design.
Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating
voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We
develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for
die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be
used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the
knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology
prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS
technology.
The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control
the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data
causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power
dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of
secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of
super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these
flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful
recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while
taking the process variations impact and robustness requirements into account.
Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward
body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases
Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and
less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each
device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a
large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for
within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability
and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of
previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital
converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real
microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability
(NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and
test chip measurements using triple-well 65nm CMOS technology.
The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process
variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We
propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative
capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access
yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of
the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results
and test chip measurements using 65nm CMOS technology
Reliability-aware memory design using advanced reconfiguration mechanisms
Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness.
Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design.
Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level.
This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens.Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean mĂĄs rĂĄpidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computaciĂłn modernas. Estos sistemas de memoria estĂĄn integrados en forma de memoria embebida para una mejor manipulaciĂłn de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual estĂĄ llegando a las dimensiones nanomĂ©tricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difĂcil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricaciĂłn - junto con la degradaciĂłn de los dispositivos - principalmente inducido por el elevado campo elĂ©ctrico y altas temperaturas - son dos de las mĂĄs relevantes amenazas que no pueden ni deben ser ignoradas por mĂĄs tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria mĂĄs utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanomĂ©trico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores estĂĄn atrayendo una elevada atenciĂłn como posibles candidatos para reemplazar las actuales tecnologĂas de memorias convencionales. A pesar de sus caracterĂsticas favorables, tales como el bajo consumo como la alta escabilidad, ellos tambiĂ©n padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradaciĂłn de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilizaciĂłn de tĂ©cnicas de reconfiguraciĂłn avanzada. La consideraciĂłn de nuevas estrategias de reconfiguraciĂłn han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbarÂż, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas tĂ©cnicas incluyen circuitos de monitorizaciĂłn para comprobar la fiabilidad de las unidades de memoria, y la implementaciĂłn arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuraciĂłn mucho mĂĄs fiables antes de que el fallo suced
Multi-criteria optimization for energy-efficient multi-core systems-on-chip
The steady down-scaling of transistor dimensions has made possible the evolutionary progress leading to todayâs high-performance multi-GHz microprocessors and core based System-on-Chip (SoC) that offer superior performance, dramatically reduced cost per function, and much-reduced physical size compared to their predecessors. On the negative side, this rapid scaling however also translates to high power densities, higher operating temperatures and reduced reliability making it imperative to address design issues that have cropped up in its wake. In particular, the aggressive physical miniaturization have increased CMOS fault sensitivity to the extent that many reliability constraints pose threat to the device normal operation and accelerate the onset of wearout-based failures. Among various wearout-based failure mechanisms, Negative biased temperature instability (NBTI) has been recognized as the most critical source of device aging.
The urge of reliable, low-power circuits is driving the EDA community to develop new design techniques, circuit solutions, algorithms, and software, that can address these critical issues. Unfortunately, this challenge is complicated by the fact that power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on compact architectures, scaled supply voltages, and small devices.
This dissertation focuses on methodologies to bridge this gap and establishes an important link between low-power solutions and aging effects. More specifically, we proposed new architectural solutions based on power management strategies to enable the design of low-power, aging aware cache memories.
Cache memories are one of the most critical components for warranting reliable and timely operation. However, they are also more susceptible to aging effects. Due to symmetric structure of a memory cell, aging occurs regardless of the fact that a cell (or word) is accessed or not. Moreover, aging is a worst-case matric and line with worst-case access pattern determines the aging of the entire cache. In order to stop the aging of a memory cell, it must be put into a proper idle state when a cell (or word) is not accessed which require proper management of the idleness of each atomic unit of power management.
We have proposed several reliability management techniques based on the idea of cache partitioning to alleviate NBTI-induced aging and obtain joint energy and lifetime benefits. We introduce graceful degradation mechanism which allows different cache blocks into which a cache is partitioned to age at different rates. This implies that various sub-blocks become unreliable at different times, and the cache keeps functioning with reduced efficiency. We extended the capabilities of this architecture by integrating the concept of reconfigurable caches to maintain the performance of the cache throughout its lifetime. By this strategy, whenever a block becomes unreliable, the remaining cache is reconfigured to work as a smaller size cache with only a marginal degradation of performance.
Many mission-critical applications require guaranteed lifetime of their operations and therefore the hardware implementing their functionality. Such constraints are usually enforced by means of various reliability enhancing solutions mostly based on redundancy which are not energy-friendly. In our work, we have proposed a novel cache architecture in which a smart use of cache partitions for redundancy allows us to obtain cache that meet a desired lifetime target with minimal energy consumption
Degradation Models and Optimizations for CMOS Circuits
Die GewĂ€hrleistung der ZuverlĂ€ssigkeit von CMOS-Schaltungen ist derzeit eines der gröĂten Herausforderungen beim Chip- und Schaltungsentwurf. Mit dem Ende der Dennard-Skalierung erhöht jede neue Generation der Halbleitertechnologie die elektrischen Felder innerhalb der Transistoren. Dieses stĂ€rkere elektrische Feld stimuliert die DegradationsphĂ€nomene (Alterung der Transistoren, Selbsterhitzung, Rauschen, usw.), was zu einer immer stĂ€rkeren Degradation (Verschlechterung) der Transistoren fĂŒhrt. Daher erleiden die Transistoren in jeder neuen Technologiegeneration immer stĂ€rkere Verschlechterungen ihrer elektrischen Parameter. Um die FunktionalitĂ€t und ZuverlĂ€ssigkeit der Schaltung zu wahren, wird es daher unerlĂ€sslich, die Auswirkungen der geschwĂ€chten Transistoren auf die Schaltung prĂ€zise zu bestimmen.
Die beiden wichtigsten Auswirkungen der Verschlechterungen sind ein verlangsamtes Schalten, sowie eine erhöhte Leistungsaufnahme der Schaltung. Bleiben diese Auswirkungen unberĂŒcksichtigt, kann die verlangsamte Schaltgeschwindigkeit zu Timing-Verletzungen fĂŒhren (d.h. die Schaltung kann die Berechnung nicht rechtzeitig vor Beginn der nĂ€chsten Operation abschlieĂen) und die FunktionalitĂ€t der Schaltung beeintrĂ€chtigen (fehlerhafte Ausgabe, verfĂ€lschte Daten, usw.). Um diesen Verschlechterungen der Transistorparameter im Laufe der Zeit Rechnung zu tragen, werden Sicherheitstoleranzen eingefĂŒhrt. So wird beispielsweise die Taktperiode der Schaltung kĂŒnstlich verlĂ€ngert, um ein langsameres Schaltverhalten zu tolerieren und somit Fehler zu vermeiden. Dies geht jedoch auf Kosten der Performanz, da eine lĂ€ngere Taktperiode eine niedrigere Taktfrequenz bedeutet. Die Ermittlung der richtigen Sicherheitstoleranz ist entscheidend. Wird die Sicherheitstoleranz zu klein bestimmt, fĂŒhrt dies in der Schaltung zu Fehlern, eine zu groĂe Toleranz fĂŒhrt zu unnötigen PerformanzseinbuĂen.
Derzeit verlĂ€sst sich die Industrie bei der ZuverlĂ€ssigkeitsbestimmung auf den schlimmstmöglichen Fall (maximal gealterter Schaltkreis, maximale Betriebstemperatur bei minimaler Spannung, ungĂŒnstigste Fertigung, etc.). Diese Annahme des schlimmsten Falls garantiert, dass der Chip (oder integrierte Schaltung) unter allen auftretenden Betriebsbedingungen funktionsfĂ€hig bleibt. DarĂŒber hinaus ermöglicht die Betrachtung des schlimmsten Falles viele Vereinfachungen. Zum Beispiel muss die eigentliche Betriebstemperatur nicht bestimmt werden, sondern es kann einfach die schlimmstmögliche (sehr hohe) Betriebstemperatur angenommen werden.
Leider lĂ€sst sich diese etablierte Praxis der BerĂŒcksichtigung des schlimmsten Falls (experimentell oder simulationsbasiert) nicht mehr aufrechterhalten. Diese BerĂŒcksichtigung bedingt solch harsche Betriebsbedingungen (maximale Temperatur, etc.) und Anforderungen (z.B. 25 Jahre Betrieb), dass die Transistoren unter den immer stĂ€rkeren elektrischen Felder enorme Verschlechterungen erleiden. Denn durch die Kombination an hoher Temperatur, Spannung und den steigenden elektrischen Feldern bei jeder Generation, nehmen die DegradationphĂ€nomene stetig zu. Das bedeutet, dass die unter dem schlimmsten Fall bestimmte Sicherheitstoleranz enorm pessimistisch ist und somit deutlich zu hoch ausfĂ€llt. Dieses MaĂ an Pessimismus fĂŒhrt zu erheblichen PerformanzseinbuĂen, die unnötig und demnach vermeidbar sind. WĂ€hrend beispielsweise militĂ€rische Schaltungen 25 Jahre lang unter harschen Bedingungen arbeiten mĂŒssen, wird Unterhaltungselektronik bei niedrigeren Temperaturen betrieben und muss ihre FunktionalitĂ€t nur fĂŒr die Dauer der zweijĂ€hrigen Garantie aufrechterhalten. FĂŒr letzteres können die Sicherheitstoleranzen also deutlich kleiner ausfallen, um die Performanz deutlich zu erhöhen, die zuvor im Namen der ZuverlĂ€ssigkeit aufgegeben wurde.
Diese Arbeit zielt darauf ab, maĂgeschneiderte Sicherheitstoleranzen fĂŒr die einzelnen Anwendungsszenarien einer Schaltung bereitzustellen. FĂŒr fordernde Umgebungen wie Weltraumanwendungen (wo eine Reparatur unmöglich ist) ist weiterhin der schlimmstmögliche Fall relevant. In den meisten Anwendungen, herrschen weniger harsche Betriebssbedingungen (z.B. sorgen KĂŒhlsysteme fĂŒr niedrigere Temperaturen). Hier können Sicherheitstoleranzen maĂgeschneidert und anwendungsspezifisch bestimmt werden, sodass Verschlechterungen exakt toleriert werden können und somit die ZuverlĂ€ssigkeit zu minimalen Kosten (Performanz, etc.) gewahrt wird.
Leider sind die derzeitigen Standardentwurfswerkzeuge fĂŒr diese anwendungsspezifische Bestimmung der Sicherheitstoleranz nicht gut gerĂŒstet. Diese Arbeit zielt darauf ab, Standardentwurfswerkzeuge in die Lage zu versetzen, diesen Bedarf an ZuverlĂ€ssigkeitsbestimmungen fĂŒr beliebige Schaltungen unter beliebigen Betriebsbedingungen zu erfĂŒllen. Zu diesem Zweck stellen wir unsere ForschungsbeitrĂ€ge als vier Schritte auf dem Weg zu anwendungsspezifischen Sicherheitstoleranzen vor:
Schritt 1 verbessert die Modellierung der DegradationsphĂ€nomene (Transistor-Alterung, -Selbsterhitzung, -Rauschen, etc.). Das Ziel von Schritt 1 ist es, ein umfassendes, einheitliches Modell fĂŒr die DegradationsphĂ€nomene zu erstellen. Durch die Verwendung von materialwissenschaftlichen Defektmodellierungen werden die zugrundeliegenden physikalischen Prozesse der DegradationsphĂ€nomena modelliert, um ihre Wechselwirkungen zu berĂŒcksichtigen (z.B. PhĂ€nomen A kann PhĂ€nomen B beschleunigen) und ein einheitliches Modell fĂŒr die simultane Modellierung verschiedener PhĂ€nomene zu erzeugen. Weiterhin werden die jĂŒngst entdeckten PhĂ€nomene ebenfalls modelliert und berĂŒcksichtigt. In Summe, erlaubt dies eine genaue Degradationsmodellierung von Transistoren unter gleichzeitiger BerĂŒcksichtigung aller essenziellen PhĂ€nomene.
Schritt 2 beschleunigt diese Degradationsmodelle von mehreren Minuten pro Transistor (Modelle der Physiker zielen auf Genauigkeit statt Performanz) auf wenige Millisekunden pro Transistor. Die ForschungsbeitrĂ€ge dieser Dissertation beschleunigen die Modelle um ein Vielfaches, indem sie zuerst die Berechnungen so weit wie möglich vereinfachen (z.B. sind nur die Spitzenwerte der Degradation erforderlich und nicht alle Werte ĂŒber einem zeitlichen Verlauf) und anschlieĂend die ParallelitĂ€t heutiger Computerhardware nutzen. Beide AnsĂ€tze erhöhen die Auswertungsgeschwindigkeit, ohne die Genauigkeit der Berechnung zu beeinflussen.
In Schritt 3 werden diese beschleunigte Degradationsmodelle in die Standardwerkzeuge integriert. Die Standardwerkzeuge berĂŒcksichtigen derzeit nur die bestmöglichen, typischen und schlechtestmöglichen Standardzellen (digital) oder Transistoren (analog). Diese drei Typen von Zellen/Transistoren werden von der Foundry (Halbleiterhersteller) aufwendig experimentell bestimmt. Da nur diese drei Typen bestimmt werden, nehmen die Werkzeuge keine ZuverlĂ€ssigkeitsbestimmung fĂŒr eine spezifische Anwendung (Temperatur, Spannung, AktivitĂ€t) vor. Simulationen mit Degradationsmodellen ermöglichen eine Bestimmung fĂŒr spezifische Anwendungen, jedoch muss diese FĂ€higkeit erst integriert werden. Diese Integration ist eines der BeitrĂ€ge dieser Dissertation.
Schritt 4 beschleunigt die Standardwerkzeuge. Digitale SchaltungsentwĂŒrfe, die nicht auf Standardzellen basieren, sowie komplexe analoge Schaltungen können derzeit nicht mit analogen Schaltungssimulatoren ausgewertet werden. Ihre Performanz reicht fĂŒr solch umfangreiche Simulationen nicht aus. Diese Dissertation stellt Techniken vor, um diese Werkzeuge zu beschleunigen und somit diese umfangreichen Schaltungen simulieren zu können.
Diese ForschungsbeitrĂ€ge, die sich jeweils ĂŒber mehrere Veröffentlichungen erstrecken, ermöglichen es Standardwerkzeugen, die Sicherheitstoleranz fĂŒr kundenspezifische Anwendungsszenarien zu bestimmen. FĂŒr eine gegebene Schaltungslebensdauer, Temperatur, Spannung und AktivitĂ€t (Schaltverhalten durch Software-Applikationen) können die Auswirkungen der Transistordegradation ausgewertet werden und somit die erforderliche (weder unter- noch ĂŒberschĂ€tzte) Sicherheitstoleranz bestimmt werden. Diese anwendungsspezifische Sicherheitstoleranz, garantiert die ZuverlĂ€ssigkeit und FunktionalitĂ€t der Schaltung fĂŒr genau diese Anwendung bei minimalen PerformanzeinbuĂen
Dependable Embedded Systems
This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from todayâs points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems
Ultra Low Power Digital Circuit Design for Wireless Sensor Network Applications
Ny forskning innenfor feltet trĂ„dlĂžse sensornettverk Ă„pner for nye og innovative produkter og lĂžsninger. Biomedisinske anvendelser er blant omrĂ„dene med stĂžrst potensial og det investeres i dag betydelige belĂžp for Ă„ bruke denne teknologien for Ă„ gjĂžre medisinsk diagnostikk mer effektiv samtidig som man Ă„pner for fjerndiagnostikk basert pĂ„ trĂ„dlĂžse sensornoder integrert i et âhelsenettâ. MĂ„let er Ă„ forbedre tjenestekvalitet og redusere kostnader samtidig som brukerne skal oppleve forbedret livskvalitet som fĂžlge av Ăžkt trygghet og mulighet for Ă„ tilbringe mest mulig tid i eget hjem og unngĂ„ unĂždvendige sykehusbesĂžk og innleggelser. For Ă„ gjĂžre dette til en realitet er man avhengige av sensorelektronikk som bruker minst mulig energi slik at man oppnĂ„r tilstrekkelig batterilevetid selv med veldig smĂ„ batterier. I sin avhandling â Ultra Low power Digital Circuit Design for Wireless Sensor Network Applicationsâ har PhD-kandidat Farshad Moradi fokusert pĂ„ nye lĂžsninger innenfor konstruksjon av energigjerrig digital kretselektronikk. Avhandlingen presenterer nye lĂžsninger bĂ„de innenfor aritmetiske og kombinatoriske kretser, samtidig som den studerer nye statiske minneelementer (SRAM) og alternative minnearkitekturer. Den ser ogsĂ„ pĂ„ utfordringene som oppstĂ„r nĂ„r silisiumteknologien nedskaleres i takt med mikroprosessorutviklingen og foreslĂ„r lĂžsninger som bidrar til Ă„ gjĂžre kretslĂžsninger mer robuste og skalerbare i forhold til denne utviklingen. De viktigste konklusjonene av arbeidet er at man ved Ă„ introdusere nye konstruksjonsteknikker bĂ„de er i stand til Ă„ redusere energiforbruket samtidig som robusthet og teknologiskalerbarhet Ăžker. Forskningen har vĂŠrt utfĂžrt i samarbeid med Purdue University og vĂŠrt finansiert av Norges ForskningsrĂ„d gjennom FRINATprosjektet âMicropower Sensor Interface in Nanometer CMOS Technologyâ
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MANAGING AND LEVERAGING VARIATIONS AND NOISE IN NANOMETER CMOS
Advanced CMOS technologies have enabled high density designs at the cost of complex fabrication process. Variation in oxide thickness and Random Dopant Fluctuation (RDF) lead to variation in transistor threshold voltage Vth. Current photo-lithography process used for printing decreasing critical dimensions result in variation in transistor channel length and width. A related challenge in nanometer CMOS is that of on-chip random noise. With decreasing threshold voltage and operating voltage; and increasing operating temperature, CMOS devices are more sensitive to random on-chip noise in advanced technologies.
In this thesis, we explore novel circuit techniques to manage the impact of process variation in nanometer CMOS technologies. We also analyze the impact of on-chip noise on CMOS circuits and propose techniques to leverage or manage impact of noise based on the application. True Random Number Generator (TRNG) is an interesting cryptographic primitive that leverages on-chip noise to generate random bits; however, it is highly sensitive to process variation. We explore novel metastability circuits to alleviate the impact of variations and at the same time leverage on-chip noise sources like Random Thermal Noise and Random Telegraph Noise (RTN) to generate high quality random bits. We develop stochastic models for metastability based TRNG circuits to analyze the impact of variation and noise. The stochastic models are used to analyze and compare low power, energy efficient and lightweight post-processing techniques targeted to low power applications like System on Chip (SoC) and RFID. We also propose variation aware circuit calibration techniques to increase reliability. We extended this technique to a more generic application of designing Post-Si Tunable (PST) clock buffers to increase parametric yield in the presence of process variation. Apart from one time variation due to fabrication process, transistors undergo constant change in threshold voltage due to aging/wear-out effects and RTN. Process variation affects conventional sensors and introduces inaccuracies during measurement. We present a lightweight wear-out sensor that is tolerant to process variation and provides a fine grained wear-out sensing. A similar circuit is designed to sense fluctuation in transistor threshold voltage due to RTN. Although thermal noise and RTN are leveraged in applications like TRNG, they affect the stability of sensitive circuits like Static Random Access Memory (SRAM). We analyze the impact of on-chip noise on Bit Error Rate (BER) and post-Si test coverage of SRAM cells
Towards Computational Efficiency of Next Generation Multimedia Systems
To address throughput demands of complex applications (like Multimedia), a next-generation system designer needs to co-design and co-optimize the hardware and software layers. Hardware/software knobs must be tuned in synergy to increase the throughput efficiency. This thesis provides such algorithmic and architectural solutions, while considering the new technology challenges (power-cap and memory aging). The goal is to maximize the throughput efficiency, under timing- and hardware-constraints