The Ursinus Weekly, April 14, 1952

MSGA plans for evaluation of professors • Alumni to hear Dr. Furbay speak • Language table meets • Sophs, freshmen draw up petitions; Deadline April 16 • Plans made to stop cheating • Library acquires new books • Operetta Sari scheduled for this weekend • Cultural Olympics rate play highly • French Club entertained • Jean Shepherd speaks at annual Weekly banquet: KYW disc jockey presents radio difficulties, problems • Heads named for YMCA • Late permissions discussed in WSGA meeting • Eight members to represent Pi Gamma Mu at Albright • IRC hears Ulbricht • German Club to hold hunt • Editorials: The passive student; Truman\u27s steel seizure wrong • Dean of Men leads busy life • Bruin team drops opener by last inning Ford rally • Ed Dawkins wins in Olympic tryout • Bob Swett elected captain • Former Ursinus star honored • Vermont\u27s new citizenshttps://digitalcommons.ursinus.edu/weekly/1540/thumbnail.jp

Embedded Systems Security: On EM Fault Injection on RISC-V and BR/TBR PUF Design on FPGA

With the increased usage of embedded computers in modern life and the rapid growth of the Internet of Things (IoT), embedded systems security has become a real concern. Especially with safety-critical systems or devices that communicate sensitive data, security becomes a critical issue. Embedded computers more than others are vulnerable to hardware attacks that target the chips themselves to extract the cryptographic keys, compromise their security, or counterfeit them. In this thesis, embedded security is studied through two different areas. The first is the study of hardware attacks by investigating Electro Magnetic Fault Injection (EMFI) on a RISC-V processor. And the second is the study of the countermeasures against counterfeiting and key extraction by investigating the implementation of the Bistable Ring Physical Unclonable Function (BR-PUF) and its variant the TBR-PUF on FPGA. The experiments on a 320 MHz five-stage pipeline RISC-V core showed that with the increase of frequency and the decrease of supplied voltage, the processor becomes more susceptible to EMFI. Analysis of the effect of EMFI on different types of instructions including arithmetic and logic operations, memory operations, and flow control operations showed different types of faults including instruction skips, instructions corruption, faulted branches, and exception faults with variant probabilities. More interestingly and for the first time, multiple consecutive instructions (up to six instructions) were empirically shown to be faulted at once, which can be very devastating, compromising the effect of software countermeasures such as instruction duplication or triplication. This research also studies the hardware implementation of the BR and TBR PUFs on a Spartan-6 FPGA. A comparative study on both the automatic and manual placement implementation approaches on FPGA is presented. With the use of the settling time as a randomization source for the automatic placement, this approach showed a potential to generate PUFs with good characteristics through multiple trials. The automatic placement approach was successful in generating 4-input XOR BR and TBR PUFs with almost ideal characteristics. Moreover, optimizations on the architectural and layout levels were performed on the BR and TBR PUFs to reduce their footprint on FPGA. This research aims to advance the understanding of the EMFI effect on processors, so that countermeasures may be designed for future secure processors. Additionally, this research helps to advance the understanding of how best to design improved BR and TBR PUFs for key protection in future secure devices

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

As memory density continues to grow in modern systems, accurate analysis of SRAM stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, leading to expensive over-design and disastrous under-design. One of the central components of more accurate dynamic stability analysis is the separatrix; however, its straightforward extraction is extremely time-consuming, and efficient methods are either non-accurate or extremely difficult to implement. In this paper, we propose a novel algorithm for fast separatrix tracing of any given SRAM topology, designed with industry standard transistor models in nano-scaled technologies. The proposed algorithm is applied to both standard 6T SRAM bitcells, as well as previously proposed alternative sub-threshold bitcells, providing up to three orders-of-magnitude speedup, as compared to brute force methods. In addition, for the first time, statistical Monte Carlo separatrix distributions are plotted

An introduction to the place of comic strips in American culture

Thesis (M.S.)--Boston Universit

A Framework for Noise Analysis and Verification of Analog Circuits

Analog circuit design and verification face significant challenges due to circuit complexity and short market windows. In particular, the influence of technology parameters on circuits, noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the various circuit blocks or it could be inherited from the circuit elements. Current industrial designs rely heavily on simulation techniques, but ensuring the correctness of such designs under all circumstances usually becomes impractically expensive. In this PhD thesis, we propose a methodology for modeling and verification of analog designs in the presence of noise and process variation using run-time verification methods. Verification based on run-time techniques employs logical or statistical monitors to check if an execution (simulation) of the design model violates the design specifications (properties). In order to study the random behavior of noise, we propose an approach based on modeling the designs using stochastic differential equations (SDE) in the time domain. Then, we define assertion and statistical verification methods in a MATLAB SDE simulation framework for monitoring properties of interest in order to detect errors. In order to overcome some of the drawbacks associated with monitoring techniques, we define a pattern matching based verification method for qualitative estimation of the simulation traces. We illustrate the efficiency of the proposed methods on different benchmark circuits

Nonlinear microscopy for failure analysis of CMOS integrated circuits in the vectorial focusing regime

This thesis focuses on the development of techniques for enhancing the spatial resolution and localisation precision in the sub-surface microscopy for failure analysis in semiconductor integrated circuits (ICs). Highest spatial resolutions are obtained by implementing solid immersion lenses (SIL), which provide unsurpassed numerical aperture (NA) for sub-surface microscopy. These high NA conditions mean that scalar diffraction theory is no longer valid and a vectorial focusing description should be applied to accurately describe the focal plane electric field distribution. Vectorial theory predicts that under high NA conditions a linearly polarised (LP) light focuses to a spot that is extended along the electric field vector, but radially polarised (RP) light is predicted to form a circular spot whose diameter equals the narrower dimension obtained with linear polarisation. By implementing a novel liquid-crystal (LC) radial polarisation converter (RPC) this effect was studied for both two-photon optical-beam-induced current (TOBIC) microscopy and two-photon laser assisted device alteration (2pLADA) techniques, showing a resolution and localisation improvement using the RP beam. By comparing images of the same structural features obtained using linear, circular and radial polarisations imaging and localisation resolutions both approaching 100 nm were demonstrated. The obtained experimental results were in good agreement with modelling and were consistent with theoretically predicted behaviour. Certain artefacts were observed under radial polarisation, which were thought to result from the extended depth of focus and the significant longitudinal field component. In any application these effects must be considered alongside the benefits of the symmetric field distribution in the focal plane. While SIL sub-surface microscopy offers unmatched spatial resolutions, it is prone to being severely degraded by aberrations arising from inaccurate dimensions of the SIL, imprecise substrate thickness or imperfect contact between SIL and substrate. It is in this context that techniques to identify and even mitigate aberrations in the system are important. A simple approach is demonstrated for revealing the presence of chromatic and spherical aberrations by measuring the two-photon autocorrelation of the pulses at the focal plane inside the sample. In the case of aberration free imaging, it was shown both theoretically and experimentally that the planes of the maximum autocorrelation amplitude and shortest pulse duration always coincide. Therefore, the optics of the imaging system can be first adjusted to obtain the minimum autocorrelation duration and then the wavefront of incident light modified to maximise the autocorrelation intensity, iterating this procedure until the positions of minimum pulse duration and maximum autocorrelation amplitude coincide

Modeling Robustness Tradeoffs in Yeast Cell Polarization Induced by Spatial Gradients

Cells localize (polarize) internal components to specific locations in response to external signals such as spatial gradients. For example, yeast cells form a mating projection toward the source of mating pheromone. There are specific challenges associated with cell polarization including amplification of shallow external gradients of ligand to produce steep internal gradients of protein components (e.g. localized distribution), response over a broad range of ligand concentrations, and tracking of moving signal sources. In this work, we investigated the tradeoffs among these performance objectives using a generic model that captures the basic spatial dynamics of polarization in yeast cells, which are small. We varied the positive feedback, cooperativity, and diffusion coefficients in the model to explore the nature of this tradeoff. Increasing the positive feedback gain resulted in better amplification, but also produced multiple steady-states and hysteresis that prevented the tracking of directional changes of the gradient. Feedforward/feedback coincidence detection in the positive feedback loop and multi-stage amplification both improved tracking with only a modest loss of amplification. Surprisingly, we found that introducing lateral surface diffusion increased the robustness of polarization and collapsed the multiple steady-states to a single steady-state at the cost of a reduction in polarization. Finally, in a more mechanistic model of yeast cell polarization, a surface diffusion coefficient between 0.01 and 0.001 µm2/s produced the best polarization performance, and this range is close to the measured value. The model also showed good gradient-sensitivity and dynamic range. This research is significant because it provides an in-depth analysis of the performance tradeoffs that confront biological systems that sense and respond to chemical spatial gradients, proposes strategies for balancing this tradeoff, highlights the critical role of lateral diffusion of proteins in the membrane on the robustness of polarization, and furnishes a framework for future spatial models of yeast cell polarization