Power Decoding Reed--Solomon Codes Up to the Johnson Radius

Power decoding, or "decoding using virtual interleaving" is a technique for decoding Reed--Solomon codes up to the Sudan radius. Since the method's inception, it has been an open question if it is possible to use this approach to decode up to the Johnson radius -- the decoding radius of the Guruswami--Sudan algorithm. In this paper we show that this can be done by incorporating a notion of multiplicities. As the original Power decoding, the proposed algorithm is a one-pass algorithm: decoding follows immediately from solving a shift-register type equation, which we show can be done in quasi-linear time. It is a "partial bounded-distance decoding algorithm" since it will fail to return a codeword for a few error patterns within its decoding radius; we investigate its failure behaviour theoretically as well as give simulation results. This is an extended version where we also show how the method can be made faster using the re-encoding technique or a syndrome formulation.Comment: Extended version of paper accepted for Advances in Mathematics of Communication. Results announced at ACCT-1

Synthesis-by-analysis of BCH Codes

In this paper we propose a technique to blindly synthesize the generator polynomial of BCH codes. The proposed technique involves finding Greatest Common Divisor (GCD) among different codewords and block lengths. Based on this combinatorial GCD calculation, correlation values are found. For a valid block length, the iterative GCD calculation results either into generator polynomial or some of its higher order multiples. These higher order polynomials are factorized under modulo-2 operation, and one of the resulting factors is always the generator polynomial which further increases the correlation value. The resulting correlation plot for different polynomials shows very high values for correct block length and valid generator polynomial. Knowing the valid block length and generator polynomial, all other parameters including number of parity-check digits (n-k), minimum distance dmin and error correcting capability t are readily exposed

Power Decoding of Reed-Solomon Codes Revisited

Power decoding, or "decoding by virtual interleaving", of Reed--Solomon codes is a method for unique decoding beyond half the minimum distance. We give a new variant of the Power decoding scheme, building upon the key equation of Gao. We show various interesting properties such as behavioural equivalence to the classical scheme using syndromes, as well as a new bound on the failure probability when the powering degree is 3.Comment: This is a major revision of the previous version: it contains a new bound on the failure probability, while some previous parts have been considerably shortened. Submitted to ICMCTA 201

A linear complexity analysis of quadratic residues and primitive roots spacings

We investigate the linear complexities of the periodic 0-1 infinite sequences in which the periods are the sequence of the parities of the spacings between quadratic residues modulo a prime p, and the sequence of the parities of the spacings between primitive roots modulo p, respectively. In either case, the Berlekamp-Massey algorithm running on MAPLE computer algebra software shows very good to perfect linear complexities.Comment: 12 page

Linear complexity of quaternary sequences over Z4 based on Ding-Helleseth generalized cyclotomic classes

A family of quaternary sequences over Z4 is defined based on the Ding-Helleseth generalized cyclotomic classes modulo pq for two distinct odd primes p and q. The linear complexity is determined by computing the defining polynomial of the sequences, which is in fact connected with the discrete Fourier transform of the sequences. The results show that the sequences possess large linear complexity and are good sequences from the viewpoint of cryptography

Automatic oscillator frequency control system

A frequency control system makes an initial correction of the frequency of its own timing circuit after comparison against a frequency of known accuracy and then sequentially checks and corrects the frequencies of several voltage controlled local oscillator circuits. The timing circuit initiates the machine cycles of a central processing unit which applies a frequency index to an input register in a modulo-sum frequency divider stage and enables a multiplexer to clock an accumulator register in the divider stage with a cyclical signal derived from the oscillator circuit being checked. Upon expiration of the interval, the processing unit compares the remainder held as the contents of the accumulator against a stored zero error constant and applies an appropriate correction word to a correction stage to shift the frequency of the oscillator being checked. A signal from the accumulator register may be used to drive a phase plane ROM and, with periodic shifts in the applied frequency index, to provide frequency shift keying of the resultant output signal. Interposition of a phase adder between the accumulator register and phase plane ROM permits phase shift keying of the output signal by periodic variation in the value of a phase index applied to one input of the phase adder

Optimal Shuffle Code with Permutation Instructions

During compilation of a program, register allocation is the task of mapping program variables to machine registers. During register allocation, the compiler may introduce shuffle code, consisting of copy and swap operations, that transfers data between the registers. Three common sources of shuffle code are conflicting register mappings at joins in the control flow of the program, e.g, due to if-statements or loops; the calling convention for procedures, which often dictates that input arguments or results must be placed in certain registers; and machine instructions that only allow a subset of registers to occur as operands. Recently, Mohr et al. proposed to speed up shuffle code with special hardware instructions that arbitrarily permute the contents of up to five registers and gave a heuristic for computing such shuffle codes. In this paper, we give an efficient algorithm for generating optimal shuffle code in the setting of Mohr et al. An interesting special case occurs when no register has to be transferred to more than one destination, i.e., it suffices to permute the contents of the registers. This case is equivalent to factoring a permutation into a minimal product of permutations, each of which permutes up to five elements.Comment: 20 pages, 5 figures, full version of a paper accepted at WADS'15. Minor update: fixed typos, corrected comma placemen

Embedding of Deterministic Test Data for In-Field Testing

This paper presents a new feedback shift register-based method for embedding deterministic test patterns on-chip suitable for complementing conventional BIST techniques for in-field testing. Our experimental results on 8 real designs show that the presented approach outperforms the bit-flipping approach by 24.7% on average. We also show that it is possible to exploit the uneven distribution of don't care bits in test patterns in order to reduce the area required for storing deterministic test patterns more than 3 times with less than 2% fault coverage drop

On Newton-Raphson iteration for multiplicative inverses modulo prime powers

We study algorithms for the fast computation of modular inverses. Newton-Raphson iteration over $p$-adic numbers gives a recurrence relation computing modular inverse modulo $p^m$, that is logarithmic in $m$. We solve the recurrence to obtain an explicit formula for the inverse. Then we study different implementation variants of this iteration and show that our explicit formula is interesting for small exponent values but slower or large exponent, say of more than $700$ bits. Overall we thus propose a hybrid combination of our explicit formula and the best asymptotic variants. This hybrid combination yields then a constant factor improvement, also for large exponents

A stochastic computing architecture for iterative estimation

Stochastic computing (SC) is a promising candidate for fault tolerant computing in digital circuits. We present a novel stochastic computing estimation architecture allowing to solve a large group of estimation problems including least squares estimation as well as sparse estimation. This allows utilizing the high fault tolerance of stochastic computing for implementing estimation algorithms. The presented architecture is based on the recently proposed linearized-Bregman-based Sparse Kaczmarz algorithm. To realize this architecture, we develop a shrink function in stochastic computing and analytically describe its error probability. We compare the stochastic computing architecture to a fixed-point binary implementation and present bit-true simulation results as well as synthesis results demonstrating the feasibility of the proposed architecture for practical implementation