Ion beam sputtering method for progressive reduction of nanostructures dimensions

An ion beam based dry etching method has been developed for progressive reduction of dimensions of prefabricated nanostructures. The method has been successfully applied to aluminum nanowires and aluminum single electron transistors (SET). The method is based on removal of material from the structures when exposed to energetic argon ions and it was shown to be applicable multiple times to the same sample. The electrical measurements and samples imaging in between the sputtering sessions clearly indicated that the dimensions, i.e. cross-section of the nanowires and area of the tunnel junctions in SET, were progressively reduced without noticeable degradation of the sample structure. We were able to reduce the effective diameter of aluminum nanowires from ~65 nm down to ~30 nm, whereas the tunnel junction area has been reduced by 40 %

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling