Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Analysis and Simulation of Active Filters Using Operational Transconductance Amplifier (OTA)

As the transistors are continuously scaling down, it becomes necessary to reduce voltage supply and power requirements of the circuit to increase its performance and stability. Whereas, current- mode devices require less number of stages with high output impedance results in improved performance and large bandwidth as compared to voltage-mode techniques. OTA are current-mode device that takes voltage as input and produces current as output with high gain and large bandwidth. The frequency bands were parameters were determined such as the cutoff frequency (fc), the band width (BW), the quality factor (Q), and the angular frequency (Wo). In this paper the design and the simulation of the transfer function has been done by using (MATLAB) in order to obtain the frequency response for all types of filter (the low pass filter, high pass filter, band pass filter and band stop filter)

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

New mathematical formulation for designing a fully differential self-biased folded cascode amplifier

One of the most important building blocks in analog circuit design is the operational amplifiers. This is because of their versatility and wide spread usage in many applications such as communications transmitters and receivers, analog to digital converters, or any other application that requires a small signal to be amplified. The basic amplifier topologies are introduced. Then, some operational amplifiers topologies are introduced with some techniques to self bias these amplifiers. The folded cascode fully differential Op-Amp with self bias is presented. This is one of the newest amplifier topologies which provide stable self-biased amplifiers. A new mathematical model for fully differential folded cascode amplifiers is presented and generalized to include the family of fully differential complementary amplifiers. This formulation focuses on deriving detailed design equations for the amplifier gain and frequency response. The equations are verified through time domain and frequency domain simulations of different fabrication processes to ensure the validity of the model across a wide range of processes. The model was verified against TMSC 180nm, 250nm, and 350nm fabrication processes. The new model agrees well with simulations; with 1% error for the amplifier gain and \u3c7% error for amplifier bandwidth. The relatively high error value for the bandwidth is because the model considers the worst case scenario and overestimates the output capacitance. Finally, the algorithm of getting this formulation is extended to include special and commonly used cases. This formulation proved to be very useful in designing stable, self-biased, fully differential folded cascode amplifiers