Serialized Asynchronous Links for NoC

This paper proposes an asynchronous serialized link for NoC that can achieve the same levels of performance in terms of flits per second as a synchronous link but with a reduced number of wires in the point to point switch links and reduced power consumption. This is achieved by employing serialization in the asynchronous domain as opposed to synchronous to facilitate the removal of global clocking on the serial links. Based on transistor level simulations using 0.12 ?m foundry models it has been shown that it is possible to achieve the same level of performance as synchronous but with 75% reduction in wires and 65% reduction in power for a 300 MFlit/s link with 8 buffers with a switch clock speed of 300 MHz. Furthermore the paper presents the design requirements arising from interfacing switches of synchronous NoC and asynchronous serial links

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links

This work investigates the application of serialization as a means of reducing the number of wires in NoC combined with asynchronous links in order to simplify the clocking of the link. Throughput is reduced but savings in routing area and reduction in power could make this attractiv

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links

This work investigates the application of serialization as a means of reducing the number of wires in NoC combined with asynchronous links in order to simplify the clocking of the link. Throughput is reduced but savings in routing area and reduction in power could make this attractiv

An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip

The demand for IP reuse and system level scalability in System-on-Chip (SoC) designs is growing. Network-onchip (NoC) constitutes a viable solution space to emerging SoC design challenges. In this paper we describe an OCP compliant network adapter (NA) architecture for the MANGO NoC. The NA decouples communication and computation, providing memory-mapped OCP transactions based on primitive message-passing services of the network. Also, it facilitates GALS-type systems, by adapting to the clockless network. This helps leverage a modular SoC design flow. We evaluate performance and cost of 0.13 µm CMOS standard cell instantiations of the architecture. I

Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect

As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration of multiple die on a single chip. Communication between die requires full network-on-chip (NoC) which is area intensive. In deep sub-micron process nodes, high speed signaling between multiple die becomes one of the main challenges in multidie chip design. Methods to increase the routability have been proposed as the use of parallel interconnect appears to be the bottleneck of high speed multidie communication. Conversion of parallel data bits into serial data streams before transmission effectively reduced the number of wires required for the interconnect. Synchronous serial transmission requires large design dimension and power hungry auxiliary blocks for synchronization between the transmitted data and clock signals. This is avoided with the implementation of self-timed transmission scheme which eliminates the need to transmit the clock signal in a separate wire. This research is conducted to develop a reusable, scalable and configurable clockless version of SerDes system as the interconnect between multiple die. The proposed design achieves a data rate of 2 Gbps small area 38.71 μm² with architectural simplicity with 308 transistor count and low power consumption of 1.10 mW

Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs

This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 um