Capsule endoscopy system with novel imaging algorithms

Wireless capsule endoscopy (WCE) is a state-of-the-art technology to receive images of human intestine for medical diagnostics. In WCE, the patient ingests a specially designed electronic capsule which has imaging and wireless transmission capabilities inside it. While the capsule travels through the gastrointestinal (GI) tract, it captures images and sends them wirelessly to an outside data logger unit. The data logger stores the image data and then they are transferred to a personal computer (PC) where the images are reconstructed and displayed for diagnosis. The key design challenge in WCE is to reduce the area and power consumption of the capsule while maintaining acceptable image reconstruction. In this research, the unique properties of WCE images are identified by analyzing hundreds of endoscopic images and video frames, and then these properties are used to develop novel and low complexity compression algorithms tailored for capsule endoscopy. The proposed image compressor consists of a new YEF color space converter, lossless prediction coder, customizable chrominance sub-sampler and an efficient Golomb-Rice encoder. The scheme has both lossy and lossless modes and is further customized to work with two lighting modes – conventional white light imaging (WLI) and emerging narrow band imaging (NBI). The average compression ratio achieved using the proposed lossy compression algorithm is 80.4% for WBI and 79.2% for NBI with high reconstruction quality index for both bands. Two surveys have been conducted which show that the reconstructed images have high acceptability among medical imaging doctors and gastroenterologists. The imaging algorithms have been realized in hardware description language (HDL) and their functionalities have been verified in field programmable gate array (FPGA) board. Later it was implemented in a 0.18 μm complementary metal oxide semiconductor (CMOS) technology and the chip was fabricated. Due to the low complexity of the core compressor, it consumes only 43 µW of power and 0.032 mm2 of area. The compressor is designed to work with commercial low-power image sensor that outputs image pixels in raster scan fashion, eliminating the need of significant input buffer memory. To demonstrate the advantage, a prototype of the complete WCE system including an FPGA based electronic capsule, a microcontroller based data logger unit and a Windows based image reconstruction software have been developed. The capsule contains the proposed low complexity image compressor and can generate both lossy and lossless compressed bit-stream. The capsule prototype also supports both white light imaging (WLI) and narrow band imaging (NBI) imaging modes and communicates with the data logger in full duplex fashion, which enables configuring the image size and imaging mode in real time during the examination. The developed data logger is portable and has a high data rate wireless connectivity including Bluetooth, graphical display for real time image viewing with state-of-the-art touch screen technology. The data are logged in micro SD cards and can be transferred to PC or Smartphone using card reader, USB interface, or Bluetooth wireless link. The workstation software can decompress and show the reconstructed images. The images can be navigated, marked, zoomed and can be played as video. Finally, ex-vivo testing of the WCE system has been done in pig's intestine to validate its performance

Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform

Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs) and general-purpose processors (GPPs) designs are viable solution for software defined radio (SDR) technology. This thesis demonstrates a practical design and implementation procedure for building a useful, efficient and flexible model of a bit error rate tester (BERT) on physical layer for UHF-band of the digital transceivers by using new architecture in Multi-Core Software-Defined Radi

Development of a Nanosatellite Software Defined Radio Communications System

Communications systems designed with application-specific integrated circuit (ASIC) technology suffer from one very significant disadvantage - the integrated circuits do not possess the ability of programmability. However, Software Defined Radio’s (SDR’s) integrated with Field Programmable Gate Arrays (FPGA) provide an opportunity to update the communication system on nanosatellites (which are physically difficult to access) due to their capability of performing signal processing in software. SDR signal processing is performed in software on reprogrammable elements such as FPGA’s. Applying this technique to nanosatellite communications systems will optimize the operations of the hardware, and increase the flexibility of the system. In this research a transceiver algorithm for a nanosatellite software defined radio communications is designed. The developed design is capable of modulation of data to transmit information and demodulation of data to receive information. The transceiver algorithm also works at different baud rates. The design implementation was successfully tested with FPGA-based hardware to demonstrate feasibility of the transceiver design with a hardware platform suitable for SDR implementation

Scalable High-Speed Communications for Neuromorphic Systems

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting in output packet loss. Also, the FX3 is unable to scale to support larger single-chip or multi-chip configurations. To alleviate communication limitations and to expand scalability, a new communications solution is presented which takes advantage of the GTX/GTH high-speed serial transceivers found on Xilinx FPGAs. A Xilinx VC707 evaluation kit is used to prototype the new communications board. The high-speed transceivers are used to communicate to the host computer via PCIe and to communicate to the DANNA arrays with the link layer protocol Aurora. The new communications board is able to outperform the FX3, reducing the latency in the communication and increasing the throughput of data. This new communications setup will be used to further DANNA research by allowing the DANNA arrays to scale to larger sizes and for multiple DANNA arrays to be connected to a single communication board

A PCIe-based readout and control board to interface with new-generation detectors for the LHC upgrade

Questa tesi si riferisce principalmente al lavoro di design, sviluppo, produzione e validazione di una nuova scheda PCIe, chiamata Pixel-ROD (Pixel Read Out Driver), come naturale prosecuzione della precedente serie di schede di readout, oggi montate nel Pixel Detector di ATLAS. In modo particolare, questa scheda è stata pensata come evoluzione per l’elettronica off-detector presente ad ATLAS, la quale è principalmente composta da schede VME, conosciute come Back Of Crate (BOC) e Read Out Driver (ROD). Inoltre, tutte le schede ROD sono state commissionate e disegnate dal Laboratorio di Progettazione Elettronica dell’INFN e del DIFA a Bologna. Il progetto della scheda Pixel-ROD è cominciato due anni fa, poichè il trend generale per l’evoluzione dell’elettronica off-detector di LHC è quello di abbandonare la più vecchia interfaccia VME, per passare a quelle più nuove e veloci (come il PCIe). Inoltre, poichè i rivelatori di ATLAS e CMS saranno accomunati dallo stesso chip di readout che interfaccerà i futuri Pixel Detector, la Pixel-ROD potrebbe essere usata non solo per l’evoluzione di ATLAS ma anche per altri esperimenti. La caratteristica principale della Pixel-ROD è la possibilità di utilizzo sia come scheda di readout singola, sia in una catena reale di acquisizione dati, che si interfaccia con dispositivi di terze parti. Il lavoro che ho svolto in questa tesi si concentra principalmente sul design, lo sviluppo e l’ottimizzazione della scheda prima della sua fabbricazione. Dopo questa fase, utilizzando i prototipi prodotti, mi sono concentrato sul lavoro di test e validazione dei singoli componenti e delle singole interfacce montate sulla scheda. Questa fase non è ancora terminata e richiede molto tempo per essere svolta, a causa della complessità dell’elettronica che è presente sulla Pixel-ROD

Development of Trigger and Control Systems for CMS

During the year of 2007, the Large Hadron Collider (LHC) and its four main detectors will begin operation with a view to answering the most pressing questions in particle physics. However before one can analyse the data produced to find the rare phenomena being looked for, both the detector and readout electronics must be thoroughly tested to ensure that the system will operate in a consistent way. The Compact Muon Solenoid (CMS) is one of the two general-purpose detectors at CERN. The tracking component of the design produces more data than any previous detector used in particle physics, with approximately ten million detector channels. The data from the detector is processed by the tracker Front End Driver (FED). The large data volume necessitated the development of a buffering and throttling system to prevent buffer overflow both on and off the detector. A critical component of this system is the APV emulator (APVe), which vetoes trigger decisions based on buffer status in the tracker. The commissioning of these components, along with a large part of the Timing, Trigger and Control (TTC) system is discussed, including the various modifications that were made to improve the robustness of the full system. Another key piece of the CMS electronics is the calorimeter trigger system, responsible for identifying âinteresting' physical events in a background of well-understood phenomena using calorimetric information. Calorimeter information is processed to identify various trigger objects by the Global Calorimeter Trigger (GCT). The first component of this system is the Source card, which has been developed to transfer data from the Regional Calorimeter Trigger (RCT) to the Leaf card, the processing engine of the GCT. The use of modern programmable logic with high speed optical links is discussed, emphasising its use for data concentration and the benefit it confers to the processing algorithms. Looking forward to Super-LHC, a possible addition to the CMS Level-1 trigger system is discussed, incorporating information from a new pixel detector with an alternative stacked geometry that allows the possibility of on-detector data rate reduction by means of a transverse momentum cut. A toy Monte Carlo was developed to study detector performance. Issues with high-speed reconstruction and the complications of on-detector data rate reduction are also discussed

Control, Readout and Commissioning of the Ultra-High Speed 1 Megapixel DSSC X-Ray Camera for the European XFEL

The goal of this thesis was to develop the software and firmware basis to control and read out the 1-Megapixel DEPFET Sensor with Signal Compression (DSSC) detector, which is being built for the European XFEL (EuXFEL). The DSSC detector proposes single photon resolution at 0.5 keV photon energy, high dynamic range of 10000 photons at a very high frame rate of 4.5 MHz. During this thesis, the readout chain has been implemented, which receives the average data rate of 134 GBit/s from the detector and transfers sorted image data via four QSFP+ fiber cables to the DAQ system. Additional control software and firmware has been developed for commissioning of the first 1/16th megapixel prototypes. A multifunctional measurement and data analysis framework has been created which is used for characterization of the detector, particularly of properties of the complex readout ASICs. Additional parameter trimming routines to automatically adapt gain and offset parameters of a large pixel matrix have been developed in order to generate suitable configurations which have been applied during two measurement campaigns at the Petra III synchrotron. For integration into the new Karabo framework, which is provided by XFEL for beamline control, several software devices have been implemented

FPGA based reconfigurable body area network using Nios II and uClinux

This research is focused on identifying an appropriate design for a reconfigurable Body Area Network (BAN). In order to investigate the benefits and drawbacks of the proposed design, a BAN system prototype was built. This system consists of two distinct node types: a slave node and a master node. These nodes communicate using ZigBee radio transceivers. The microcontroller-based slave node acquires sensor data and transmits digitized samples to the master node. The master node is FPGA-based and runs uClinux on a soft-core microcontroller. The purpose of the master node is to receive, process and store digitized sensor data. In order to verify the operation of the BAN system prototype and demonstrate reconfigurability, a specific application was required. Pattern recognition in electrocardiogram (ECG) data was the application used in this work and the MIT-BIH Arrhythmia Database was used as the known data source for verification. A custom test platform was designed and built for the purpose of injecting data from the MIT-BIH Arrhythmia Database into the BAN system. The BAN system designed and built in this work demonstrates the ability to record raw ECG data, detect R-peaks, calculate and record R-R intervals, detect premature ventricular and atrial contractions. As this thesis will identify, many aspects of this BAN system were designed to be highly reconfigurable allowing it to be used for a wide range of BAN applications, in addition to pattern recognition of ECG data

Development of electronics for the VELO upgrade detector

Esta tesis cubre el diseño electrónico del detector de vértices (VELO) del experimento LHCb del CERN. El VELO está situado rodeando el punto de colisión de los dos haces de protones del LHC del CERN. Su diseño está lleno de restricciones que requieren diseños novedosos: minimizar la materia cerca del punto de colisión, diseño de componentes que soporten radiación, transmisión de datos a alta tasa y el procesado de los mismos, sincronización del sistema, etc. El trabajo presentado en esta tesis se centra en: por un lado, la validación del hardware y sus diferentes prototipos, por otro lado, el diseño del firmware de las FPGAs encargadas del control, sincronización y adquisición de datos del VELO