73 research outputs found

    Design, Modeling and Analysis of Non-classical Field Effect Transistors

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    Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

    Strain-Engineered MOSFETs

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    This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

    Miniaturized Transistors, Volume II

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    In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

    Caractérisation, mécanismes et applications mémoire des transistors avancés sur SOI

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    Ce travail prĂ©sente les principaux rĂ©sultats obtenus avec une large gamme de dispositifs SOI avancĂ©s, candidats trĂšs prometteurs pour les futurs gĂ©nĂ©rations de transistors MOSFETs. Leurs propriĂ©tĂ©s Ă©lectriques ont Ă©tĂ© analysĂ©es par des mesures systĂ©matiques, agrĂ©mentĂ©es par des modĂšles analytiques et/ou des simulations numĂ©riques. Nous avons Ă©galement proposĂ© une utilisation originale de dispositifs FinFETs fabriquĂ©s sur ONO enterrĂ© en fonctionnalisant le ONO Ă  des fins d'application mĂ©moire non volatile, volatile et unifiĂ©es. AprĂšs une introduction sur l'Ă©tat de l'art des dispositifs avancĂ©s en technologie SOI, le deuxiĂšme chapitre a Ă©tĂ© consacrĂ© Ă  la caractĂ©risation dĂ©taillĂ©e des propriĂ©tĂ©s de dispositifs SOI planaires ultra- mince (Ă©paisseur en dessous de 7 nm) et multi-grille. Nous avons montrĂ© l excellent contrĂŽle Ă©lectrostatique par la grille dans les transistors trĂšs courts ainsi que des effets intĂ©ressants de transport et de couplage. Une approche similaire a Ă©tĂ© utilisĂ©e pour Ă©tudier et comparer des dispositifs FinFETs Ă  double grille et triple grille. Nous avons dĂ©montrĂ© que la configuration FinFET double grille amĂ©liore le couplage avec la grille arriĂšre, phĂ©nomĂšne important pour des applications Ă  tension de seuil multiple. Nous avons proposĂ© des modĂšles originaux expliquant l'effet de couplage 3D et le comportement de la mobilitĂ© dans des TFTs nanocristallin ZnO. Nos rĂ©sultats ont soulignĂ© les similitudes et les diffĂ©rences entre les transistors SOI et Ă  base de ZnO. Des mesures Ă  basse tempĂ©rature et de nouvelles mĂ©thodes d'extraction ont permis d'Ă©tablir que la mobilitĂ© dans le ZnO et la qualitĂ© de l'interface ZnO/SiO2 sont remarquables. Cet Ă©tat de fait ouvre des perspectives intĂ©ressantes pour l'utilisation de ce type de matĂ©riaux aux applications innovantes de l'Ă©lectronique flexible. Dans le troisiĂšme chapitre, nous nous sommes concentrĂ©s sur le comportement de la mobilitĂ© dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnĂ©torĂ©sistance Ă  basse tempĂ©rature. Nous avons mis en Ă©vidence expĂ©rimentalement un comportement de mobilitĂ© inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre rĂ©sultat original concerne l existence et l interprĂ©tation de la magnĂ©torĂ©sistance gĂ©omĂ©trique dans les FinFETs.L'utilisation de FinFETs fabriquĂ©s sur ONO enterrĂ© en tant que mĂ©moire non volatile flash a Ă©tĂ© proposĂ©e dans le quatriĂšme chapitre. Deux mĂ©canismes d'injection de charge ont Ă©tĂ© Ă©tudiĂ©s systĂ©matiquement. En plus de la dĂ©monstration de la pertinence de ce type mĂ©moire en termes de performances (rĂ©tention, marge de dĂ©tection), nous avons mis en Ă©vidence un comportement inattendu : l amĂ©lioration de la marge de dĂ©tection pour des dispositifs Ă  canaux courts. Notre concept innovant de FinFlash sur ONO enterrĂ© prĂ©sente plusieurs avantages: (i) opĂ©ration double-bit et (ii) sĂ©paration de la grille de stockage et de l'interface de lecture augmentant la fiabilitĂ© et autorisant une miniaturisation plus poussĂ©e que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons explorĂ© le concept de mĂ©moire unifiĂ©e, en combinant les opĂ©rations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterrĂ©. Comme escomptĂ© pour les mĂ©moires dites unifiĂ©es, le courant transitoire en mode 1T-DRAM dĂ©pend des charges non volatiles stockĂ©es dans le ONO. D'autre part, nous avons montrĂ© que les charges piĂ©gĂ©es dans le nitrure ne sont pas perturbĂ©es par les opĂ©rations de programmation et lecture de la 1T-DRAM. Les performances de cette mĂ©moire unifiĂ©e multi-bits sont prometteuses et pourront ĂȘtre considĂ©rablement amĂ©liorĂ©es par optimisation technologique de ce dispositif.The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.SAVOIE-SCD - Bib.Ă©lectronique (730659901) / SudocGRENOBLE1/INP-Bib.Ă©lectronique (384210012) / SudocGRENOBLE2/3-Bib.Ă©lectronique (384219901) / SudocSudocFranceF

    Journal of Telecommunications and Information Technology, 2007, nr 2

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    Defect Induced Aging and Breakdown in High-k Dielectrics

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    abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

    Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

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    The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO2 was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA). MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO2/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (Rs) associated with the substrate and metal contact. The interface state density (Dit), calculated by conductance method, suggests that Dit is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit whereas crystallized HfO2 has the highest Dit. Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples. The reliability of TiN/ZrO2/Al2O3/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO2 by SPAO when SPAO is processed after high-k. GeO2 at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress. To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces

    FiliĂšre technologique hybride InGaAs/SiGe pour applications CMOS

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    High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.Les materiaux Ă  forte mobilitĂ© comme l’InGaAs et le SiGe sont considĂ©rĂ©s comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux dĂ©fis doivent ĂȘtre surmontĂ©s pour transformer ce concept en rĂ©alitĂ© industrielle. Cette thĂšse couvre les principaux challenges que sont l’intĂ©gration de l’InGaAs sur Si, la formation d’oxydes de grille de qualitĂ©, la rĂ©alisation de rĂ©gions source/drain auto-alignĂ©es de faible rĂ©sistance, l’architecture des transistors ou encore la co-intĂ©gration de ces matĂ©riaux dans un procĂ©dĂ© de fabrication CMOS.Les solutions envisagĂ©es sont proposĂ©es en gardant comme ligne directrice l’applicabilitĂ© des mĂ©thodes pour une production de grande envergure.Le chapitre 2 aborde l’intĂ©gration d’InGaAs sur Si par deux mĂ©thodes diffĂ©rentes. Le chapitre3 dĂ©taille le dĂ©veloppement de modules spĂ©cifiques Ă  la fabrication de transistors auto-alignĂ©s sur InGaAs. Le chapitre 4 couvre la rĂ©alisation de diffĂ©rents types de transistors auto-alignĂ©s sur InGaAs dans le but d’amĂ©liorer leurs performances. Enfin, le chapitre 5 prĂ©sente trois mĂ©thodes diffĂ©rentes pour rĂ©aliser des circuits hybrides CMOS Ă  base d’InGaAs et de SiGe
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