Physical Layer Techniques for High Frequency Wireline Broadband Systems

This thesis collects contributions to wireline and wireless communication systems with an emphasis on multiuser and multicarrier physical layer technology. To deliver increased capacity, modern wireline access systems such as G.fast extend the signal bandwidth up from tens to hundreds of MHz. This ambitious development revealed a number of unforeseen hurdles such as the impact of impedance changes in various forms. Impedance changes have a strong effect on the performance of multi-user crosstalk mitigation techniques such as vectoring. The first part of the thesis presents papers covering the identification of one of these problems, a model describing why it occurs and a method to mitigate its effects, improving line stability for G.fast systems.A second part of the thesis deals with the effects of temperature changes on wireline channels. When a vectored (MIMO) wireline system is initialized, channel estimates need to be obtained. This thesis presents contributions on the feasibility of re-using channel coefficients to speed up the vectoring startup procedures, even after the correct coefficients have changed, e.g., due to temperature changes. We also present extensive measurement results showing the effects of temperature changes on copper channels using a temperature chamber and British cables. The last part of the thesis presents three papers on the convergence of physical layer technologies, more specifically the deployment of OFDM-based radio systems using twisted pairs in different ways. In one proposed scenario, the idea of using the access copper lines to deploy small cells inside users' homes is explored. The feasibility of the concept, the design of radio-heads and a practical scheme for crosstalk mitigation are presented in three contributions

Bandwidth Compressed Waveform and System Design for Wireless and Optical Communications: Theory and Practice

This thesis addresses theoretical and practical challenges of spectrally efficient frequency division multiplexing (SEFDM) systems in both wireless and optical domains. SEFDM improves spectral efficiency relative to the well-known orthogonal frequency division multiplexing (OFDM) by non-orthogonally multiplexing overlapped sub-carriers. However, the deliberate violation of orthogonality results in inter carrier interference (ICI) and associated detection complexity, thus posing many challenges to practical implementations. This thesis will present solutions for these issues. The thesis commences with the fundamentals by presenting the existing challenges of SEFDM, which are subsequently solved by proposed transceivers. An iterative detection (ID) detector iteratively removes self-created ICI. Following that, a hybrid ID together with fixed sphere decoding (FSD) shows an optimised performance/complexity trade-off. A complexity reduced Block-SEFDM can subdivide the signal detection into several blocks. Finally, a coded Turbo-SEFDM is proved to be an efficient technique that is compatible with the existing mobile standards. The thesis also reports the design and development of wireless and optical practical systems. In the optical domain, given the same spectral efficiency, a low-order modulation scheme is proved to have a better bit error rate (BER) performance when replacing a higher order one. In the wireless domain, an experimental testbed utilizing the LTE-Advanced carrier aggregation (CA) with SEFDM is operated in a realistic radio frequency (RF) environment. Experimental results show that 40% higher data rate can be achieved without extra spectrum occupation. Additionally, a new waveform, termed Nyquist-SEFDM, which compresses bandwidth and suppresses out-of-band power leakage is investigated. A 4th generation (4G) and 5th generation (5G) coexistence experiment is followed to verify its feasibility. Furthermore, a 60 GHz SEFDM testbed is designed and built in a point-to-point indoor fiber wireless experiment showing 67% data rate improvement compared to OFDM. Finally, to meet the requirements of future networks, two simplified SEFDM transceivers are designed together with application scenarios and experimental verifications

Energy efficient visible light communications relying on amorphous cells

In this paper, we design an energy efficient indoor Visible Light Communications (VLC) system from a radically new perspective based on an amorphous user-to-network association structure. Explicitly, this intriguing problem is approached from three inter-linked perspectives, considering the cell formation, link-level transmission and system-level optimisation, critically appraising the related optical constraints. To elaborate, apart from proposing hitherto unexplored Amorphous Cells (A-Cells), we employ a powerful amalgam of Asymmetrically Clipped Optical Orthogonal Frequency Division Multiplexing (ACO-OFDM) and transmitter pre-coding aided Multi-Input Single-Output (MISO) transmission. As far as the overall systemlevel optimisation is concerned, we propose a low-complexity solution dispensing with the classic Dinkelbach’s algorithmic structure. Our numerical study compares a range of different cell formation strategies and investigates diverse design aspects of the proposed A-Cells. Specifically, our results show that the A-Cells proposed are capable of achieving a much higher energy efficiency per user compared to that of the conventional cell formation for a range of practical Field of Views (FoVs) angles

Oversampled analog-to-digital converter architectures based on pulse frequency modulation

Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development of voltage-controlled oscillator based analog-to-digital converters (VCO-based ADCs). Time-encoding based ADCs have become of great interest to the designer community due to the possibility of implementing mostly digital circuits, which are well suited for current deep-submicron CMOS processes. Within this topic, VCO-based ADCs are one of the most promising candidates. VCO-based ADCs have typically been analyzed considering the output phase of the oscillator as a state variable, similar to the state variables considered in __ modulation loops. Although this assumption might take us to functional designs (as verified by literature), it does not take into account neither the oscillation parameters of the VCO nor the deterministic nature of quantization noise. To overcome this issue, we propose an interpretation of these type of systems based on the pulse frequency modulation (PFM) theory. This permits us to analytically calculate the quantization noise, in terms of the working parameters of the system. We also propose a linear model that applies to VCO-based systems. Thanks to it, we can determine the different error processes involved in the digitization of the input data, and the performance limitations which these processes direct to. A generic model for any order open-loop VCO-based ADCs is made based on the PFM theory. However, we will see that only the first-order case and a second order approximation can be implemented in practice. The PFM theory also allows us to propose novel approaches to both single-stage and multistage VCObased architectures. We describe open-loop architectures such as VCO-based architectures with digital precoding, PFM-based architectures that can be used as efficient ADCs or MASH architectures with optimal noise-transfer-function (NTF) zeros. We also make a first approach to the proposal and analysis of closed loop architectures. At the same time, we deal with one of the main limitations of VCOs (especially those built with ring oscillators), which is the non-linear voltage to- frequency relation. In this document, we describe two techniques mitigate this phenomenon. Firstly, we propose to use a pulse width modulator in front of the VCO. This way, there are only two possible oscillation states. Consequently, the oscillator works linearly. To validate the proposed technique, an experimental prototype was implemented in a 40-nm CMOS process. The chip showed noise problems that degraded the expected resolution, but allowed us to verify that the potential performance was close to the expected one. A potential signal-to-noise-distortion ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming 2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar power consumption and linearity properties. Secondly, we used a pulse frequency modulator to implement a second ADC. The proposed architecture is intrinsically linear and uses a digital delay line to increase the resolution of the converter. One experimental prototype was implemented in a 40-nm CMOS process using one of these architectures. Proper results were measured from this prototype. These results allowed us to verify that the PFM-based architecture could be used as an efficient ADC. The measured peak SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an occupied area equal to 0.08 mm2. The architecture shows a great linearity, and in comparison to related work, it consumes less power and occupies similar area. In general, the theoretical analyses and the architectures proposed in the document are not restricted to any application. Nevertheless, in the case of the experimental chips, the specifications required for these converters were linked to communication applications (e.g. VDSL, VDSL2, or even G.fast), which means medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva para el diseño de convertidores analógico-digitales basados en osciladores controlados por tensión. Los convertidores analógico-digitales con codificación temporal han llamado la atención durante los últimos años de la comunidad de diseñadores debido a la posibilidad de implementarlos en su gran mayoría con circuitos digitales, los cuales son muy apropiados para los procesos de diseño manométricos. En este ámbito, los convertidores analógico-digitales basados en osciladores controlados por tensión son uno de los candidatos más prometedores. Los convertidores analógico-digitales basados en osciladores controlados por tensión han sido típicamente analizados considerando que la fase del oscilador es una variable de estado similar a las que se observan en los moduladores __. Aunque esta consideración puede llevarnos a diseños funcionales (como se puede apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de la modulación por frecuencia de pulsos. Esto nos permite calcular de forma analítica las ecuaciones que modelan el ruido de cuantificación en función de los parámetros de oscilación. Se propone también un modelo lineal para el análisis de convertidores analógico-digitales basados en osciladores controlados por tensión. Este modelo permite determinar las diferentes fuentes de error que se producen durante el proceso de digitalización de los datos de entrada y las limitaciones que suponen. Un modelo genérico de convertidor de cualquier orden se propone con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una aproximación al caso de segundo orden se pueden implementar en la práctica. La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas para la propuesta y el análisis tanto de arquitecturas de una sola etapa como de arquitecturas de varias etapas construidas con osciladores controlados por tensión. Se proponen y se describen arquitecturas en lazo abierto como son las basadas en osciladores controlador por tensión con moduladores digitales en la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como convertidores analógico-digitales eficientes o arquitecturas en cascada en las que se optimizan la distribución de los ceros en la función de transferencia del ruido. También se realiza una aproximación a la propuesta y el análisis de arquitecturas en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes de los osciladores controlados por tensión (especialmente en aquellos implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos técnicas cuyo objetivo es mitigar esta limitación. La primera técnica de corrección se basa en el uso de un modulador por ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y no se genera distorsión en los datos de salida. La técnica se propone de forma teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo la validación de la propuesta teórica se fabricó un prototipo experimental en un proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo que se mantiene el consumo así como la linealidad. A continuación, se propone la implementación de un convertidor analógico digital mediante un modulador por frecuencia de pulsos. La arquitectura propuesta es intrínsecamente lineal y hace uso de una línea de retraso digital con el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental, se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura, de la que se obtuvieron resultados notables. Estos resultados permitieron verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor analógico-digital eficiente. La arquitectura consigue una relación real señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en comparación con arquitecturas equivalentes, el consumo es menor mientras que el área ocupada se mantiene similar. En general, las aportaciones propuestas en este documento se pueden aplicar a cualquier tipo de aplicación, independientemente de los requisitos de resolución, ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones (VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media (9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman

D6.3 Intermediate system evaluation results

The overall purpose of METIS is to develop a 5G system concept that fulfil s the requirements of the beyond-2020 connected information society and to extend today’s wireless communication systems for new usage cases. First, in this deliverable an updated view on the overall METIS 5G system concept is presented. Thereafter, simulation results for the most promising technology components supporting the METIS 5G system concept are reported. Finally, s imulation results are presented for one relevant aspect of each Horizontal Topic: Direct Device - to - Device Communication, Massive Machine Communication, Moving Networks, Ultra - Dense Networks, and Ultra - Reliable Communication.Popovski, P.; Mange, G.; Fertl, P.; Gozálvez - Serrano, D.; Droste, H.; Bayer, N.; Roos, A.... (2014). D6.3 Intermediate system evaluation results. http://hdl.handle.net/10251/7676

Unmanned Aerial Vehicle (UAV)-Enabled Wireless Communications and Networking

The emerging massive density of human-held and machine-type nodes implies larger traffic deviatiolns in the future than we are facing today. In the future, the network will be characterized by a high degree of flexibility, allowing it to adapt smoothly, autonomously, and efficiently to the quickly changing traffic demands both in time and space. This flexibility cannot be achieved when the network’s infrastructure remains static. To this end, the topic of UAVs (unmanned aerial vehicles) have enabled wireless communications, and networking has received increased attention. As mentioned above, the network must serve a massive density of nodes that can be either human-held (user devices) or machine-type nodes (sensors). If we wish to properly serve these nodes and optimize their data, a proper wireless connection is fundamental. This can be achieved by using UAV-enabled communication and networks. This Special Issue addresses the many existing issues that still exist to allow UAV-enabled wireless communications and networking to be properly rolled out