On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute- and power-intensive structure of Neural Networks (NNs), hardware accelerators emerge as a promising solution. However, with technology node scaling below 10nm, hardware accelerators become more susceptible to faults, which in turn can impact the NN accuracy. In this paper, we study the resilience aspects of Register-Transfer Level (RTL) model of NN accelerators, in particular, fault characterization and mitigation. By following a High-Level Synthesis (HLS) approach, first, we characterize the vulnerability of various components of RTL NN. We observed that the severity of faults depends on both i) application-level specifications, i.e., NN data (inputs, weights, or intermediate), NN layers, and NN activation functions, and ii) architectural-level specifications, i.e., data representation model and the parallelism degree of the underlying accelerator. Second, motivated by characterization results, we present a low-overhead fault mitigation technique that can efficiently correct bit flips, by 47.3% better than state-of-the-art methods.Comment: 8 pages, 6 figure

Comparative Analysis among DSP and FPGA-based Control Capabilities in PWM Power Converters

PWM power converters are close to be mature for standard diffusion. New FPGA technologies could now realise at best the digital control key-points: flexible performance and time to market. The paper deals with the new digital control properties of FPGA-based techniques. On the basis of reference structures, a comparative analysis is carried-out trading-off dynamic performances and immunity to PWM environment. All possible sampled control or DSP techniques are firstly analysed and compared to each other. A breakthrough concept for FPGAs is defined, definitely solving for PWM feedback immunity by practical over-sampling and parallel processing while improving dynamic performances. Simulation tests and the application of dead-beat control clearly point-out the respective dynamic properties

The Effelsberg-Bonn HI Survey (EBHIS)

The Effelsberg-Bonn HI survey (EBHIS) comprises an all-sky survey north of Dec = -5 degrees of the Milky Way and the local volume out to a red-shift of z ~ 0.07. Using state of the art Field Programmable Gate Array (FPGA) spectrometers it is feasible to cover the 100 MHz bandwidth with 16.384 spectral channels. High speed storage of HI spectra allows us to minimize the degradation by Radio Frequency Interference (RFI) signals. Regular EBHIS survey observations started during the winter season 2008/2009 after extensive system evaluation and verification tests. Until today, we surveyed about 8000 square degrees, focusing during the first all-sky coverage of the Sloan-Digital Sky Survey (SDSS) area and the northern extension of the Magellanic stream. The first whole sky coverage will be finished in 2011. Already this first coverage will reach the same sensitivity level as the Parkes Milky Way (GASS) and extragalactic surveys (HIPASS). EBHIS data will be calibrated, stray-radiation corrected and freely accessible for the scientific community via a web-interface. In this paper we demonstrate the scientific data quality and explore the expected harvest of this new all-sky survey.Comment: 19 pages, 11 figures, accepted for publication by Astronomical Note

A committee machine gas identification system based on dynamically reconfigurable FPGA

This paper proposes a gas identification system based on the committee machine (CM) classifier, which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. The CM combines five different classifiers: K nearest neighbors (KNNs), multilayer perceptron (MLP), radial basis function (RBF), Gaussian mixture model (GMM), and probabilistic principal component analysis (PPCA). Experiments on real sensors' data proved the effectiveness of our system with an improved accuracy over individual classifiers. Due to the computationally intensive nature of CM, its implementation requires significant hardware resources. In order to overcome this problem, we propose a novel time multiplexing hardware implementation using a dynamically reconfigurable field programmable gate array (FPGA) platform. The processing is divided into three stages: sampling and preprocessing, pattern recognition, and decision stage. Dynamically reconfigurable FPGA technique is used to implement the system in a sequential manner, thus using limited hardware resources of the FPGA chip. The system is successfully tested for combustible gas identification application using our in-house tin-oxide gas sensors

A reconfigurable real-time morphological system for augmented vision

There is a significant number of visually impaired individuals who suffer sensitivity loss to high spatial frequencies, for whom current optical devices are limited in degree of visual aid and practical application. Digital image and video processing offers a variety of effective visual enhancement methods that can be utilised to obtain a practical augmented vision head-mounted display device. The high spatial frequencies of an image can be extracted by edge detection techniques and overlaid on top of the original image to improve visual perception among the visually impaired. Augmented visual aid devices require highly user-customisable algorithm designs for subjective configuration per task, where current digital image processing visual aids offer very little user-configurable options. This paper presents a highly user-reconfigurable morphological edge enhancement system on field-programmable gate array, where the morphological, internal and external edge gradients can be selected from the presented architecture with specified edge thickness and magnitude. In addition, the morphology architecture supports reconfigurable shape structuring elements and configurable morphological operations. The proposed morphology-based visual enhancement system introduces a high degree of user flexibility in addition to meeting real-time constraints capable of obtaining 93 fps for high-definition image resolution

An FPGA-based infant monitoring system

We have designed an automated visual surveillance system for monitoring sleeping infants. The low-level image processing is implemented on an embedded Xilinx’s Virtex II XC2v6000 FPGA and quantifies the level of scene activity using a specially designed background subtraction algorithm. We present our algorithm and show how we have optimised it for this platform