System level performance and yield optimisation for analogue integrated circuits

Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield.This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype.For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse.A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology

Fast and Robust Design of CMOS VCO for Optimal Performance

The exponentially growing design complexity with technological advancement calls for a large scope in the analog and mixed signal integrated circuit design automation. In the automation process, performance optimization under different environmental constraints is of prime importance. The analog integrated circuits design strongly requires addressing multiple competing performance objectives for optimization with ability to find global solutions in a constrained environment. The integrated circuit (IC) performances are significantly affected by the device, interconnect and package parasitics. Inclusion of circuit parasitics in the design phase along with performance optimization has become a bare necessity for faster prototyping. Besides this, the fabrication process variations have a predominant effect on the circuit performance, which is directly linked to the acceptability of manufactured integrated circuit chips. This necessitates a manufacturing process tolerant design. The development of analog IC design methods exploiting the computational intelligence of evolutionary techniques for optimization, integrating the circuit parasitic in the design optimization process in a more meaningful way and developing process fluctuation tolerant optimal design is the central theme of this thesis. Evolutionary computing multi-objective optimization techniques such as Non-dominated Sorting Genetic Algorithm-II and Infeasibility Driven Evolutionary Algorithm are used in this thesis for the development of parasitic aware design techniques for analog ICs. The realistic physical and process constraints are integrated in the proposed design technique. A fast design methodology based on one of the efficient optimization technique is developed and an extensive worst case process variation analysis is performed. This work also presents a novel process corner variation aware analog IC design methodology, which would effectively increase the yield of chips in the acceptable performance window. The performance of all the presented techniques is demonstrated through the application to CMOS ring oscillators, current starved and xi differential voltage controlled oscillators, designed in Cadence Virtuoso Analog Design Environment

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology

In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout- and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a multi-objective optimization algorithm to achieve a Pareto-optimal front containing optimal circuit designs offering different performance trade-offs. The final outcome of the proposed methodology is a set of design solutions (with their GDSII description available and ready-to-fabricate) that need no further designer intervention. Two key elements of the proposed methodology are the use of an optimization algorithm linked to an off-the-shelf simulator and an inductor model that yield EM-like accuracy but with much shorter evaluation times. Furthermore, the methodology guarantees the same high level of robustness against layout parasitics and variability that an expert designer would achieve with the verification tools at his/her disposal. The methodology is technology-independent and can be used for the design of radio frequency circuits. The results are validated with experimental measurements on a physical prototype

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm). Post-layout simulation results for a case of study with typical jitter of 68fs for a 1.8V 80dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.Gobierno de España TEC2015-68448-REuropean Space Agency 4000108445-13-NL-R

Multi-objective Digital VLSI Design Optimisation

Modern VLSI design's complexity and density has been exponentially increasing over the past 50 years and recently reached a stage within its development, allowing heterogeneous, many-core systems and numerous functions to be integrated into a tiny silicon die. These advancements have revealed intrinsic physical limits of process technologies in advanced silicon technology nodes. Designers and EDA vendors have to handle these challenges which may otherwise result in inferior design quality, even failures, and lower design yields under time-to-market pressure. Multiple or many design objectives and constraints are emerging during the design process and often need to be dealt with simultaneously. Multi-objective evolutionary algorithms show flexible capabilities in maintaining multiple variable components and factors in uncertain environments. The VLSI design process involves a large number of available parameters both from designs and EDA tools. This provides many potential optimisation avenues where evolutionary algorithms can excel. This PhD work investigates the application of evolutionary techniques for digital VLSI design optimisation. Automated multi-objective optimisation frameworks, compatible with industrial design flows and foundry technologies, are proposed to improve solution performance, expand feasible design space, and handle complex physical floorplan constraints through tuning designs at gate-level. Methodologies for enriching standard cell libraries regarding drive strength are also introduced to cooperate with multi-objective optimisation frameworks, e.g., subsequent hill-climbing, providing a richer pool of solutions optimised for different trade-offs. The experiments of this thesis demonstrate that multi-objective evolutionary algorithms, derived from biological inspirations, can assist the digital VLSI design process, in an industrial design context, to more efficiently search for well-balanced trade-off solutions as well as optimised design space coverage. The expanded drive granularity of standard cells can push the performance of silicon technologies with offering improved solutions regarding critical objectives. The achieved optimisation results can better deliver trade-off solutions regarding power, performance and area metrics than using standard EDA tools alone. This has been not only shown for a single circuit solution but also covered the entire standard-tool-produced design space

Numerical and Evolutionary Optimization 2020

This book was established after the 8th International Workshop on Numerical and Evolutionary Optimization (NEO), representing a collection of papers on the intersection of the two research areas covered at this workshop: numerical optimization and evolutionary search techniques. While focusing on the design of fast and reliable methods lying across these two paradigms, the resulting techniques are strongly applicable to a broad class of real-world problems, such as pattern recognition, routing, energy, lines of production, prediction, and modeling, among others. This volume is intended to serve as a useful reference for mathematicians, engineers, and computer scientists to explore current issues and solutions emerging from these mathematical and computational methods and their applications

Fiabilisation de convertisseurs analogique-numérique à modulation Sigma-Delta

This thesis concentrates on reliability-aware methodology development, reliability analysis based on simulation as well as failure prediction of CMOS 65nm analog and mixed signal (AMS) ICs. Sigma-Delta modulators are concerned as the object of reliability study at system level. A hierarchical statistical approach for reliability is proposed to analysis the performance of Sigma-Delta modulators under ageing effects and process variations. Statistical methods are combined into this analysis flow.Ce travail de thèse a porté sur des problèmes de fiabilité de circuits intégrés en technologie CMOS 65 nm, en particulier sur la conception en vue de la fiabilité, la simulation et l'amélioration de la fiabilité. Les mécanismes dominants de vieillissement HCI et NBTI ainsi que la variation du processus ont été étudiés et évalués quantitativement au niveau du circuit et au niveau du système. Ces méthodes ont été appliquées aux modulateurs Sigma-Delta afin de déterminer la fiabilité de ce type de composant qui est très utilisé

Fiabilisation de Convertisseurs Analogique-Num´erique a Modulation Sigma-Delta

Due to the continuously scaling down of CMOS technology, system-on-chips (SoCs) reliability becomes important in sub-90 nm CMOS node. Integrated circuits and systems applied to aerospace, avionic, vehicle transport and biomedicine are highly sensitive to reliability problems such as ageing mechanisms and parametric process variations. Novel SoCs with new materials and architectures of high complexity further aggravate reliability as a critical aspect of process integration. For instance, random and systematic defects as well as parametric process variations have a large influence on quality and yield of the manufactured ICs, right after production. During ICs usage time, time-dependent ageing mechanisms such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) can significantly degrade ICs performance.La fiabilit´e des ICs est d´efinie ainsi : la capacit´e d’un circuit ou un syst`eme int´egr´e `amaintenir ses param`etres durant une p´eriode donn´ee sous des conditions d´efinies. Les rapportsITRS 2011 consid`ere la fiabilit´e comme un aspect critique du processus d’int´egration.Par cons´equent, il faut faire appel des m´ethodologies innovatrices prenant en comptela fiabilit´e afin d’assurer la fonctionnalit´e du SoCs et la fiabilit´e dans les technologiesCMOS `a l’´echelle nanom´etrique. Cela nous permettra de d´evelopper des m´ethodologiesind´ependantes du design et de la technologie CMOS, en revanche, sp´ecialis´ees en fiabilit´e

SALSA: A Formal Hierarchical Optimization Framework for Smart Grid

The smart grid, by the integration of advanced control and optimization technologies, provides the traditional grid with an indisputable opportunity to deliver and utilize the electricity more efficiently. Building smart grid applications is a challenging task, which requires a formal modeling, integration, and validation framework for various smart grid domains. The design flow of such applications must adapt to the grid requirements and ensure the security of supply and demand. This dissertation, by proposing a formal framework for customers and operations domains in the smart grid, aims at delivering a smooth way for: i) formalizing their interactions and functionalities, ii) upgrading their components independently, and iii) evaluating their performance quantitatively and qualitatively.The framework follows an event-driven demand response program taking no historical data and forecasting service into account. A scalable neighborhood of prosumers (inside the customers domain), which are equipped with smart appliances, photovoltaics, and battery energy storage systems, are considered. They individually schedule their appliances and sell/purchase their surplus/demand to/from the grid with the purposes of maximizing their comfort and profit at each instant of time. To orchestrate such trade relations, a bilateral multi-issue negotiation approach between a virtual power plant (on behalf of prosumers) and an aggregator (inside the operations domain) in a non-cooperative environment is employed. The aggregator, with the objectives of maximizing its profit and minimizing the grid purchase, intends to match prosumers' supply with demand. As a result, this framework particularly addresses the challenges of: i) scalable and hierarchical load demand scheduling, and ii) the match between the large penetration of renewable energy sources being produced and consumed. It is comprised of two generic multi-objective mixed integer nonlinear programming models for prosumers and the aggregator. These models support different scheduling mechanisms and electricity consumption threshold policies.The effectiveness of the framework is evaluated through various case studies based on economic and environmental assessment metrics. An interactive web service for the framework has also been developed and demonstrated

Control and Optimization of Energy Storage in AC and DC Power Grids

Energy storage attracts attention nowadays due to the critical role it will play in the power generation and transportation sectors. Electric vehicles, as moving energy storage, are going to play a key role in the terrestrial transportation sector and help reduce greenhouse emissions. Bulk hybrid energy storage will play another critical role for feeding the new types of pulsed loads on ship power systems. However, to ensure the successful adoption of energy storage, there is a need to control and optimize the charging/discharging process, taking into consideration the customer preferences and the technical aspects. In this dissertation, novel control and optimization algorithms are developed and presented to address the various challenges that arise with the adoption of energy storage in the electricity and transportation sectors. Different decentralized control algorithms are proposed to manage the charging of a mass number of electric vehicles connected to different points of charging in the power distribution system. The different algorithms successfully satisfy the preferences of the customers without negatively impacting the technical constraints of the power grid. The developed algorithms were experimentally verified at the Energy Systems Research Laboratory at FIU. In addition to the charge control of electric vehicles, the optimal allocation and sizing of commercial parking lots are considered. A bi-layer Pareto multi-objective optimization problem is formulated to optimally allocate and size a commercial parking lot. The optimization formulation tries to maximize the profits of the parking lot investor, as well as minimize the losses and voltage deviations for the distribution system operator. Sensitivity analysis to show the effect of the different objectives on the selection of the optimal size and location is also performed. Furthermore, in this dissertation, energy management strategies of the onboard hybrid energy storage for a medium voltage direct current (MVDC) ship power system are developed. The objectives of the management strategies were to maintain the voltage of the MVDC bus, ensure proper power sharing, and ensure proper use of resources, where supercapacitors are used during the transient periods and batteries are used during the steady state periods. The management strategies were successfully validated through hardware in the loop simulation