Analysis and representation of test cases generated from LOTOS

Cataloged from PDF version of article.This paper presents a method to generate, analyse and represent test cases from protocol specification. The language of temporal ordering specification (LOTOS) is mapped into an extended finite state machine (EFSM). Test cases are generated from EFSM. The generated test cases are modelled as a dependence graph. Predicate slices are used to identify infeasible test cases that must be eliminated. Redundant assignments and predicates in all the feasible test cases are removed by reducing the test case dependence graph. The reduced test case dependence graph is adapted for a local single-layer (LS) architecture. The reduced test cases for the LS architecture are enhanced to represent the tester's behaviour. The dynamic behaviour of the test cases is represented in the form of control graphs by inverting the events, assigning verdicts to the events in the enhanced dependence graph. © 1995

Estelle-based test generation tool

A test design tool for functional analysis and test derivation of protocols formally specified using an extended finitestate machine model is presented. The formal description language supported is Estelle. The tool's main components include a compiler, a normalizer, a multiple module transition tour generator and several interactive programs. The tool is based on a static analysis of Estelle called normalization, which is explained in detail with various examples. The normalized specification facilitates graphical displays of the control and data flow in the specification by the interactive tools. Next discussed is test generation, which is based on verifying the control and data flow. First the data flow graph must be decomposed into blocks where each block represents the data flow in a protocol function. From the control graph the tool generates transition tours, and then test sequences are derived from the transition tour to test each function. The performance of the tool on various applications is also included. © 1991

Using formal methods to support testing

Formal methods and testing are two important approaches that assist in the development of high quality software. While traditionally these approaches have been seen as rivals, in recent years a new consensus has developed in which they are seen as complementary. This article reviews the state of the art regarding ways in which the presence of a formal specification can be used to assist testing

Applying Formal Methods to Networking: Theory, Techniques and Applications

Despite its great importance, modern network infrastructure is remarkable for the lack of rigor in its engineering. The Internet which began as a research experiment was never designed to handle the users and applications it hosts today. The lack of formalization of the Internet architecture meant limited abstractions and modularity, especially for the control and management planes, thus requiring for every new need a new protocol built from scratch. This led to an unwieldy ossified Internet architecture resistant to any attempts at formal verification, and an Internet culture where expediency and pragmatism are favored over formal correctness. Fortunately, recent work in the space of clean slate Internet design---especially, the software defined networking (SDN) paradigm---offers the Internet community another chance to develop the right kind of architecture and abstractions. This has also led to a great resurgence in interest of applying formal methods to specification, verification, and synthesis of networking protocols and applications. In this paper, we present a self-contained tutorial of the formidable amount of work that has been done in formal methods, and present a survey of its applications to networking.Comment: 30 pages, submitted to IEEE Communications Surveys and Tutorial

Design and implementation of a TTCN to C translator

The conformance testing of a protocol implementation, may be logically divided into, the specification of the abstract test suite (ATS) from a formal descnption of the protocol, and the subsequent derivation of the executable test suite (ETS) from the ATS specification. Our concern here is with the latter step, in particular, the automatic derivation of an ATS expressed in the Tree and Tabular Combined Notation (TTCN) to an executable C language equivalent. This process is currently a manual one, and as a consequence is error prone, time consuming, often repetitive and not necessarily consistent. To overcome these problems, there exists the real need for a computer aided, and if possible, fully automatic solution. This study descnbes the design and implementation of a fully working TTCN subset to C language translator, which takes a TTCN ATS and produces an equivalent ETS, with a minimal amount of manual intervention. The methodology used is logically divided into three stages direct TTCN to C language mappings, implementation issues, including the generation of additional code to drive the above mappings, and test system implementation issues. The system was tested using parts of an ETSI ISDN LAPD ATS and the results showed considerable time savings against a similar manual implementation. In conclusion, suggestions are provided to the further development of the TTCN to C translator system, and discussion is given to the apphcation of this tool to a complete conformance testing system

Easing the Transition from Inspiration to Implementation: A Rapid Prototyping Platform for Wireless Medium Access Control Protocols

Packet broadcast networks are in widespread use in modern wireless communication systems. Medium access control is a key functionality within such technologies. A substantial research effort has been and continues to be invested into the study of existing protocols and the development of new and specialised ones. Academic researchers are restricted in their studies by an absence of suitable wireless MAC protocol development methods. This thesis describes an environment which allows rapid prototyping and evaluation of wireless medium access control protocols. The proposed design flow allows specification of the protocol using the specification and description language (SDL) formal description technique. A tool is presented to convert the SDL protocol description into a C++ model suitable for integration into both simulation and implementation environments. Simulations at various levels of abstraction are shown to be relevant at different stages of protocol design. Environments based on the Cinderella SDL simulator and the ns-2 network simulator have been developed which allow early functional verification, along with detailed and accurate performance analysis of protocols under development. A hardware platform is presented which allows implementation of protocols with flexibility in the hardware/software trade-off. Measurement facilities are integral to the hardware framework, and provide a means for accurate real-world feedback on protocol performance

Génération automatique de cas de test pour les systèmes modélisés par des machines à états finis communicantes

Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal