Highly Automated Formal Verification of Arithmetic Circuits

This dissertation investigates the problems of two distinctive formal verification techniques for verifying large scale multiplier circuits and proposes two approaches to overcome some of these problems. The first technique is equivalence checking based on recurrence relations, while the second one is the symbolic computation technique which is based on the theory of Gröbner bases. This investigation demonstrates that approaches based on symbolic computation have better scalability and more robustness than state-of-the-art equivalence checking techniques for verification of arithmetic circuits. According to this conclusion, the thesis leverages the symbolic computation technique to verify floating-point designs. It proposes a new algebraic equivalence checking, in contrast to classical combinational equivalence checking, the proposed technique is capable of checking the equivalence of two circuits which have different architectures of arithmetic units as well as control logic parts, e.g., floating-point multipliers

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Structural optimization of numerical programs for high-level synthesis

This thesis introduces a new technique, and its associated tool SOAP, to automatically perform source-to-source optimization of numerical programs, specifically targeting the trade-off among numerical accuracy, latency, and resource usage as a high-level synthesis flow for FPGA implementations. A new intermediate representation, MIR, is introduced to carry out the abstraction and optimization of numerical programs. Equivalent structures in MIRs are efficiently discovered using methods based on formal semantics by taking into account axiomatic rules from real arithmetic, such as associativity, distributivity and others, in tandem with program equivalence rules that enable control-flow restructuring and eliminate redundant array accesses. For the first time, we bring rigorous approaches from software static analysis, specifically formal semantics and abstract interpretation, to bear on program transformation for high-level synthesis. New abstract semantics are developed to generate a computable subset of equivalent MIRs from an original MIR. Using formal semantics, three objectives are calculated for each MIR representing a pipelined numerical program: the accuracy of computation and an estimate of resource utilization in FPGA and the latency of program execution. The optimization of these objectives produces a Pareto frontier consisting of a set of equivalent MIRs. We thus go beyond existing literature by not only optimizing the precision requirements of an implementation, but changing the structure of the implementation itself. Using SOAP to optimize the structure of a variety of real world and artificially generated arithmetic expressions in single precision, we improve either their accuracy or the resource utilization by up to 60%. When applied to a suite of computational intensive numerical programs from PolyBench and Livermore Loops benchmarks, SOAP has generated circuits that enjoy up to a 12x speedup, with a simultaneous 7x increase in accuracy, at a cost of up to 4x more LUTs.Open Acces

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Automated UVM Testbench Generation Using EMF

La verifica di dispositivi digitali complessi richiede lo sviluppo di testbench che diventano sempre più complessi con un aumento continuo dei tempi di realizzazione e di manutenzione. La metodologia UVM (Universal Verification Methodology) è stata introdotta dall'industria per permettere un'astrazione dell'ambiente di verifica ed allo stesso tempo aumentare la capacità di riutilizzo dei componenti. Rimane però complicata la creazione. Questo elaborata esplora una possibile strategia, basata su EMF (Eclipse Modeling Framework), Sirius ed Acceleo, per automatizzare la stesura dei testbench. Si comincia con una presentazione di alcuni strumenti utilizzati nella verifica, quali Verilog, SystemVerilog ed UVM, seguita da una presentazione dell'insieme di strumenti che si possono utilizzare per la generazione automatica di codice. In particolare, EMF (Eclipse Modeling Framework), Sirius ed Acceleo. L'elaborato si conclude con una discussione sull'utilizzo degli strumenti nel progetto sviluppato durante il tirocinio in azienda.Verifying complex digital devices requires developing testbenches of ever growing complexity, whose creation and maintenance times keep increasing. UVM (Universal Verification Methodology) was introduced by the industry to allow the abstraction of the verification environment and, at the same time, increase reusability. Testbench creation remains complex and time consuming. This dissertation explores a possible strategy, based on EMF (Eclipse Modeling Framework), Sirius and Acceleo, for automating testbench generation. The work begins with an introduction of some of the state-of-the-art tools used in verification, i.e. Verilog, SystemVerilog and UVM, followed by an introduction to a set of tools that can be used for automatic code generation. In particular, EMF (Eclipse Modeling Framework), Sirius ed Acceleo. The dissertation concludes with a discussion on the use of the tools for a project developed during the internship