Self-checking on-line testable static RAM

This is a fault-tolerant random access memory for use in fault-tolerant computers. It comprises a plurality of memory chips each comprising a plurality of on-line testable and correctable memory cells disposed in rows and columns for holding individually addressable binary bits and provision for error detection incorporated into each memory cell for outputting an error signal whenever a transient error occurs therein. In one embodiment, each of the memory cells comprises a pair of static memory sub-cells for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the memory sub-cells to one another and for outputting the error signal whenever the contents do not match. In another embodiment, each of the memory cells comprises a static memory sub-cell and a dynamic memory sub-cell for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the static memory sub-cell to the dynamic memory sub-cell and for outputting the error signal whenever the contents do not match. Capability for correction of errors is also included

Design of Window Comparators for Integrator-Based Capacitor Array Testing Circuits

This paper investigates the impact of window comparator threshold variations on the performance of integrator-based programmable capacitor array (PCA) testing circuits. It presents two window comparator designs that take different approaches to address the problem of comparator threshold variations in PCA testing. The first comparator design utilizes a fully symmetric circuit structure to achieve small threshold deviations. The second design relies on increasing testing time to reduce the effect of comparator threshold variations. Experimental results are presented to compare the performance of the two design approaches

A Programmable Window Comparator for Analog Online Testing

This paper discusses the challenge of designing window comparators for analog online testing applications. A programmable window comparator with adaptive error threshold is presented. Experimental results demonstrate that improved fault detection capability is achieved by using the proposed design. Measurement results of the fabricated comparator circuit are also presented

Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications

This paper presents a novel window comparator circuit whose error threshold can be adaptively adjusted according to its input signal levels. It is ideal for analog online testing applications. Advantages of adaptive comparator error thresholds over constant or relative error thresholds in analog testing applications are discussed. Analytical equations for guiding the design of proposed comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS 0.18mu technology. Measurement results of the fabricated chip are presented

Preliminary design of a 100 kW turbine generator

The National Science Foundation and the Lewis Research Center have engaged jointly in a Wind Energy Program which includes the design and erection of a 100 kW wind turbine generator. The machine consists primarily of a rotor turbine, transmission, shaft, alternator, and tower. The rotor, measuring 125 feet in diameter and consisting of two variable pitch blades operates at 40 rpm and generates 100 kW of electrical power at 18 mph wind velocity. The entire assembly is placed on top of a tower 100 feet above ground level

Sport and exercise recommendations for pregnant athletes: a systematic scoping review

ObjectivesTo analyse the available evidence and identify gaps in current knowledge regarding physical activity volume and intensity and their effects on pregnancy outcomes in female athletes.DesignScoping review.Data sourcesA structured literature search of three electronic databases (Embase, PubMed and Web of Science) was conducted on 25 February 2022, and a rerun search was conducted on 8 September 2022.Eligibility criteriaStudies were eligible if they contained information on the relevant population (ie, elite or competitive amateur female athletes), intervention/exposure (ie, minimum of 10 hours of sport per week) and fetal and maternal outcomes. Eligible comparators included female recreational athletes and pregnant non-exercisers.Risk of biasThe risk of bias was evaluated with the National Institutes of Health (National Heart, Lung and Blood Institute) quality assessment tool.ResultsThe results revealed a discrepancy between the number of original research papers and the number of reviews and recommendations derived from them. The identified studies focused primarily on pregnant recreational athletes. Sixteen clinical studies met the inclusion criteria. No adverse effects on maternal or fetal outcomes were reported. Only during performance tests involving acute intensive exercise with the mother exercising at more than 90% of her maximal heart rate did some fetuses experience decelerations in heart rate.Summary/conclusionA lack of high-quality studies and direct evidence on pregnant elite and competitive amateur female athletes is evident. Further prospective observational cohort studies are needed using new monitoring methods (eg, non-invasive, wireless monitoring systems) aiming to gain a broader understanding of the stress tolerance of pregnant athletes and fetuses during exercise. Following that, interventional studies with stress tests in laboratory settings should be conducted. Therefore, technology plays a decisive role in gaining new knowledge and providing evidence-based recommendations on this topic.PROSPERO registration numberCRD42022309541

Analog Configurability-Test Scheme for an Embedded Op-Amp Module in TI MSP430 Microcontrollers

This paper proposes the application of the analog configurability test (ACT) approach for an embedded analog configurable circuit, composed by operational amplifiers and interconnection resources that are embedded in the MSP430xG461x microcontrollers family, with the aim of verifying its mode programmability. This test strategy is particularly useful for applications involving in-field circuit reconfiguration, and require reliability and safe operation characteristics. The approach minimizes the cost in hardware overhead by employing only the hardware and software resources of the microcontroller. An embedded test routine sequentially programs selected module configurations, sets the test stimulus, acquires data from the internal ADC, and performs required calculations to determine the gain of the block. The test approach is experimentally evaluated using an embedded-system based real application board. Our experimental results show very good repeatability, with very low errors. These results show that the ACT proposed here is useful for testing the functionality of the EACC under test in a real application context by using a simple strategy at a very low cost.Sociedad Argentina de Informática e Investigación Operativ

Analog Configurability-Test Scheme for an Embedded Op-Amp Module in TI MSP430 Microcontrollers

This paper proposes the application of the analog configurability test (ACT) approach for an embedded analog configurable circuit, composed by operational amplifiers and interconnection resources that are embedded in the MSP430xG461x microcontrollers family, with the aim of verifying its mode programmability. This test strategy is particularly useful for applications involving in-field circuit reconfiguration, and require reliability and safe operation characteristics. The approach minimizes the cost in hardware overhead by employing only the hardware and software resources of the microcontroller. An embedded test routine sequentially programs selected module configurations, sets the test stimulus, acquires data from the internal ADC, and performs required calculations to determine the gain of the block. The test approach is experimentally evaluated using an embedded-system based real application board. Our experimental results show very good repeatability, with very low errors. These results show that the ACT proposed here is useful for testing the functionality of the EACC under test in a real application context by using a simple strategy at a very low cost.Sociedad Argentina de Informática e Investigación Operativ

New techniques for functional testing of microprocessor based systems

Electronic devices may be affected by failures, for example due to physical defects. These defects may be introduced during the manufacturing process, as well as during the normal operating life of the device due to aging. How to detect all these defects is not a trivial task, especially in complex systems such as processor cores. Nevertheless, safety-critical applications do not tolerate failures, this is the reason why testing such devices is needed so to guarantee a correct behavior at any time. Moreover, testing is a key parameter for assessing the quality of a manufactured product. Consolidated testing techniques are based on special Design for Testability (DfT) features added in the original design to facilitate test effectiveness. Design, integration, and usage of the available DfT for testing purposes are fully supported by commercial EDA tools, hence approaches based on DfT are the standard solutions adopted by silicon vendors for testing their devices. Tests exploiting the available DfT such as scan-chains manipulate the internal state of the system, differently to the normal functional mode, passing through unreachable configurations. Alternative solutions that do not violate such functional mode are defined as functional tests. In microprocessor based systems, functional testing techniques include software-based self-test (SBST), i.e., a piece of software (referred to as test program) which is uploaded in the system available memory and executed, with the purpose of exciting a specific part of the system and observing the effects of possible defects affecting it. SBST has been widely-studies by the research community for years, but its adoption by the industry is quite recent. My research activities have been mainly focused on the industrial perspective of SBST. The problem of providing an effective development flow and guidelines for integrating SBST in the available operating systems have been tackled and results have been provided on microprocessor based systems for the automotive domain. Remarkably, new algorithms have been also introduced with respect to state-of-the-art approaches, which can be systematically implemented to enrich SBST suites of test programs for modern microprocessor based systems. The proposed development flow and algorithms are being currently employed in real electronic control units for automotive products. Moreover, a special hardware infrastructure purposely embedded in modern devices for interconnecting the numerous on-board instruments has been interest of my research as well. This solution is known as reconfigurable scan networks (RSNs) and its practical adoption is growing fast as new standards have been created. Test and diagnosis methodologies have been proposed targeting specific RSN features, aimed at checking whether the reconfigurability of such networks has not been corrupted by defects and, in this case, at identifying the defective elements of the network. The contribution of my work in this field has also been included in the first suite of public-domain benchmark networks