Self-Assembly of Electric Circuits

Self-Assembly of Electric Circuit

전자 장치 내 국부적 전계 향상을 위한 나노 구조체

학위논문(박사) -- 서울대학교대학원 : 공과대학 화학생물공학부, 2021.8. 조재영.The goal of this dissertation is to investigate effect of nanostructures for local electric field enhancement in electronic devices and to provide experimental and theoretical bases for their practical use. Resistive random access memory (RRAM) is a data storage device that can be modulated its resistance states by external electrical stimuli. The electric field generated by the applied potential difference between the two electrodes acts as the driving force to switch the resistance states, so controlling the electric field within the device can lead to improved operational performance and reliability of the device. Even though considerable progress has been made through significant efforts to control the electric field within the device, selectively enhancing the electric field in the intended position for stable and uniform resistive switching behavior is still challenging. Engineered metal structures in the RRAM can efficiently manipulate the electric field. As the radius of the metal structures decreases, the charge density increases, generating electric field enhancements in confined region. To minimize the radius of the metal structure and thus to greatly increase the electric field in a local area, we introduced a nanoscale metal structure into the RRAM. First, pyramid-structured metal electrode with a sharp tip was used to achieve a tip-enhanced electric field, and the effect of the enhanced electric field on the resistive switching behaviors of the device was investigated. Based on numerical simulation and experimental results, we confirmed that pyramidal electrode with a tip radius of tens of nanometers can selectively enhance the electric field at the tip. The tip-enhanced electric field can facilitate the thermochemical reaction in transition metal oxide-based RRAMs and efficiency of charge injection and transport in organic-based RRAMs, as well as provide position selectivity during formation of conductive filament. The resulting RRAM exhibited reliable resistive switching behavior and highly improved device performance compared with conventional RRAM with planar electrode. As another approach to enhance the electric field within the resistive switching layer, we prepared spherical nanostructures via self-assembled block copolymer (BCP)/metal compound micelles. BCP and metal precursors were dissolved in aqueous media for use as BCP/metal compound micelles. These micelles were used as complementary resistive switch (CRS) layers of the memory device and the mechanism of CRS behavior was investigated. The spherical metal nanostructures can improve the electric fields, promoting a resistive switching mechanism based on electrochemical metallization. The resulting CRS memory exhibited reliable resistive switching behavior with four distinct threshold voltages in both cycle-to-cycle and cell-to-cell tests. Also, the conduction and resistive switching mechanism are experimentally demonstrated through the the analysis of the current–voltage data plot and detemination of the temperature coefficient of resistance. Overall, we pursued efficient engineering of metal nanostructures capable of manipulating electric fields for improving the operational performance and reliability of memory devices. There is no doubt that the commercialized RRAM will become popular in the near future after overcoming all the challenges of RRAM through continuous interest and research. We believe that these results will not only contribute to the significant advancement of all electronic devices, including RRAM, but will also help promote research activities in the electronic device field.본 논문의 목적은 나노 구조체를 통한 전자 장치 내 국부적 전계 향상 효과를 조사하고, 이의 실제 사용을 위한 실험 및 이론적 기반을 제공하는 것이다. 저항변화메모리 (resistive random access memory) 는 외부 전기 자극에 의해 저항 상태를 변화 시킬 수 있는 데이터 저장 장치이다. 두 전극 사이에 인가된 전위차에 의해 생성된 전기장은 저항 상태를 전환시키는 구동력으로써 작용하므로, 전자 장치 내에서 전기장을 제어하면 장치의 성능과 신뢰성을 향상시킬 수 있다. 장치 내에서 전기장을 제어하려는 많은 노력을 통해 상당한 진전이 있었지만, 안정적이고 균일한 저항 변화 거동을 위해 의도된 위치에서 전기장을 선택적으로 향상시키는 일은 아직 도전적 과제이다. 구조화된 금속을 저항변화메모리에 접목시킴으로써 전기장을 효율적으로 조작할 수 있다. 금속 구조체의 반경이 감소함에 따라 전하 밀도가 증가하여 국부적 영역에서 전기장이 향상된다. 이 논문에서는 금속 구조체의 반경을 최소화하여 국부적으로 전기장을 크게 향상시키기 위해 저항변화메모리에 나노스케일의 금속 구조체를 도입하였다. 첫 번째로, 팁 강화 (tip-enhanced) 전기장 효과를 달성하기 위해 날카로운 팁을 가지는 피라미드 금속 구조체를 전극으로 사용하였으며, 강화된 전기장이 소자의 저항 변화 거동에 미치는 영향을 조사하였다. 유한요소모델링과 실험결과를 바탕으로, 수십 나노 미터의 팁 반경을 가지는 피라미드 구조체 전극이 팁 부근에서 전기장을 국소적으로 향상시킬 수 있음을 확인하였다. 팁 강화 전기장은 전이 금속 산화물-기반 저항변화메모리에서 열화학 (thermochemical) 반응을 촉진시키고 유기-기반 저항변화메모리에서 전하 주입 (charge injection) 및 수송 (transport) 효율성을 향상시킬 뿐 아니라, 선택적인 위치에서만 전도성 필라멘트 (conductive filament)를 형성시킬 수 있었다. 그 결과 피라미드 구조체 저항변화메모리는 종래의 평판 구조체 저항변화메모리에 비해 안정적인 저항 변화 거동과 향상된 장치 성능을 보여주었다. 저항 변화 층 내의 전기장을 향상시키기 위한 또 다른 접근법으로, 자기조립 (self-assembled)된 블록공중합체 (block copolymer)/금속 복합체 미셀 (micelle)을 이용하여 구형의 나노구조체를 소자의 중간층으로 도입하였다. 블록공중합체 및 금속전구체를 복합체 미셀로 사용하기 위해 선택적 용매에 용해시켰다. 해당 미셀을 메모리 소자의 상보적 저항 변화 (complementary resistive switch) 층으로 사용하였으며, 상보적 저항 변화 거동의 메커니즘을 조사하였다. 구형의 금속 나노구조체는 전기장을 향상시켜 전기화학적 금속화 (electrochemical metallization)에 기반한 저항 변화 메커니즘을 촉진시킬 수 있었다. 그 결과 상보적 저항 변화 메모리는 사이클 및 셀간 반복 시험 모두에서 4개의 임계 전압으로 안정적인 저항 변화 동작을 나타내었다. 또한 전류-전압 자료 플롯 (plot) 분석과 저항의 온도 계수 결정을 통해 장치의 전도 및 저항 변화 메커니즘을 실험적으로 입증하였다. 전반적으로 본 논문에서는 장치 내 전기장을 증폭시킬 수 있는 금속 나노구조체의 효율적인 엔지니어링을 통해 메모리 장치의 성능과 신뢰성 향상을 추구하였다. 지속적인 관심과 연구를 통해 저항변화메모리의 모든 과제를 극복한 후, 상용화된 저항변화메모리가 가까운 미래에 대중화될 것임을 믿어 의심치 않는다. 우리는 이 결과가 저항변화메모리를 포함한 모든 전자 장치의 획기적인 발전에 기여할 뿐만 아니라 전자 장치 분야의 연구 활동을 촉진하는 데에도 도움이 될 것이라고 믿는다.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Necessity of new memory devices 1 1.1.2. Resistive random access memory 2 1.2. Motivation 4 1.3. Dissertation Overview 6 1.4. References 9 Chapter 2. Tip-Enhanced Electric Field-Driven Efficient Charge Injection and Transport in Organic Material-Based Resistive Memories 19 2.1. Introduction 21 2.2. Experimental 24 2.3. Results and Discussion 27 2.4. Conclusions 37 2.5. References 38 Chapter 3. Facilitation of the Thermochemical Mechanism in NiO-Based Resistive Switching Memories via Tip-Enhanced Electric Fields 52 3.1. Introduction 54 3.2. Experimental 57 3.3. Results and Discussion 60 3.4. Conclusions 66 3.5. References 67 Chapter 4. Facile Achievement of Complementary Resistive Switching Behaviors via Self-Assembled Block Copolymer Micelles 82 4.1. Introduction 83 4.2. Experimental 86 4.3. Results and Discussion 89 4.4. Conclusions 96 4.5. References 97 Chapter 5. Conclusion 109 Abstract in Korean 112박

Design of bias circuit for charge pump in 130nm BiCMOS technology

El presente trabajo muestra el diseño de un circuito de polarización en la tecnología de 130nm BiCMOS con las herramientas de diseño de Cadence. El circuito de polarización es parte de un circuito Charge Pump (CP), el cual a su vez es parte de un circuito PLL (Phased Locked Loop) que se utilizará en una implementación de señal mixta de un Recuperador de Datos (CDR). Al inicio del trabajo se presenta una descripción general de los módulos analógicos y digitales que conforman el proyecto. La topología de diseño propuesta refleja la enorme dependencia del circuito de polarización con el circuito CP. Un circuito replica permite “seguir” las variaciones de carga y descarga de corriente del circuito CP para compensar mediante un OTA (Operational Transconductance Amplifier) el nivel de voltaje requerido en los transistores del circuito diferencial del CP. El proceso de diseño, la generación de esquemáticos y bancos de pruebas son mostrados durante los primeros capítulos del trabajo. La verificación del diseño pre-layout a través del proceso de esquinas, así como el uso el uso de las herramientas de verificación de reglas de diseño post-layout son mostradas durante los capítulos finales.The present work shows the design of a Bias circuit in 130 nm of BiCMOS process using Cadence tools. The Bias circuit is part of a Charge Pump (CP) circuit, which in turn is one block of a PLL (Phased Locked Loop) that will be used in a mixed-signal implementation of a Clock and Data Recovery (CDR) circuit. This PLL-based CDR is the project of the generation 2018 of the Specialty in System on a Chip at ITESO. A general description of the analog and digital modules that make up this project is shown at the beginning of this work. As it is described in detail in this work, the proposed design topology reveals the enormous dependence of the polarization circuit to the CP circuit. The replica method used in the Bias circuit allows to "follow" the current variations of CP charge/discharge process to compensate through an OTA (Operational Transconductance Amplifier) the level of voltage required by the tail transistors of CP circuit. The design procedure, the generation of schematics and test benches are shown during the first chapters of this work. The verification of the pre-layout design through the corners process, as well as the use of the post-layout design rules verification tools, are shown during the final chapters of this work.Consejo Nacional de Ciencia y Tecnologí

High-throughput large-area plastic nanoelectronics

Large-area electronics (LAE) manufacturing has been a key focus of both academic and industrial research, especially within the last decade. The growing interest is born out of the possibility of adding attractive properties (flexibility, light weight or minimal thickness) at low cost to well-established technologies, such as photovoltaics, displays, sensors or enabling the realisation of emerging technologies such as wearable devices and the Internet of Things. As such there has been great progress in the development of materials specifically designed to be employed in solution processed (plastic) electronics, including organic, transparent metal oxide and nanoscale semiconductors, as well as progress in the deposition methods of these materials using low-cost high-throughput printing techniques, such as gravure printing, inkjet printing, and roll-to-roll vacuum deposition. Meanwhile, industry innovation driven by Moore’s law has pushed conventional silicon-based electronic components to the nanoscale. The processes developed for LAE must strive to reach these dimensions. Given that the complex and expensive patterning techniques employed by the semiconductor industry so far are not compatible with LAE, there is clearly a need to develop large-area high throughput nanofabrication techniques. This thesis presents progress in adhesion lithography (a-Lith), a nanogap electrode fabrication process that can be applied over large areas on arbitrary substrates. A-Lith is a self-alignment process based on the alteration of surface energies of a starting metal electrode which allows the removal of any overlap of a secondary metal electrode. Importantly, it is an inexpensive, scalable and high throughput technique, and, especially if combined with low temperature deposition of the active material, it is fundamentally compatible with large-area fabrication of nanoscale electronic devices on flexible (plastic) substrates. Herein, I present routes towards process optimisation with a focus on gap size reduction and yield maximisation. Asymmetric gaps with sizes below 10 nm and yields of > 90 % for hundreds of electrode pairs generated on a single substrate are demonstrated. These large width electrode nanogaps represent the highest aspect ratio nanogaps (up to 108) fabricated to date. As a next step, arrays of Schottky nanodiodes are fabricated by deposition of a suitable semiconductor from solution into the nanogap structures. Of principal interest is the wide bandgap transparent semiconductor, zinc oxide (ZnO). Lateral ZnO Schottky diodes show outstanding characteristics, with on-off ratios of up to 106 and forward current values up to 10 mA for obtained upon combining a-Lith with low-temperature solution processing. These unique devices are further investigated for application in rectifier circuits, and in particular for potential use in radio frequency identification (RFID) tag technology. The ZnO diodes are found to surpass the 13.56 MHz frequency bernchmark used in commercial applications and approach the ultra-high frequency (UHF) band (hundreds of megahertz), outperforming current state of the art printed diodes. Solution processed fullerene (C60) is also shown to approach the UHF band in this co-planar device configuration, highlighting the viability of a-Lith for enabling large-area flexible radio frequency nanoelectronics. Finally, resistive switching memory device arrays based on a-Lith patterned nanogap aluminium symmetric electrodes are demonstrated for the first time. These devices are based either on empty aluminium nanogap electrodes, or with the gap filled with a solution-processed semiconductor, the latter being ZnO, the semiconducting polymer poly(9,9-dioctylfluorene-alt-benzothiadiazole) (F8BT) or carbon nanotube/polyfluorene blends. The switching mechanism, retention time and switching speed are investigated and compared with published data. The fabrication of arrays of these devices illustrates the potential of a-Lith as a simple technique for the realisation of large-area high-density memory applications.Open Acces

Threshold Switching and Self-Oscillation in Niobium Oxide

Volatile threshold switching, or current controlled negative differential resistance (CC-NDR), has been observed in a range of transition metal oxides. Threshold switching devices exhibit a large non-linear change in electrical conductivity, switching from an insulating to a metallic state under external stimuli. Compact, scalable and low power threshold switching devices are of significant interest for use in existing and emerging technologies, including as a selector element in high-density memory arrays and as solid-state oscillators for hardware-based neuromorphic computing. This thesis explores the threshold switching in amorphous NbOx and the properties of individual and coupled oscillators based on this response. The study begins with an investigation of threshold switching in Pt/NbOx/TiN devices as a function device area, NbOx film thickness and temperature, which provides important insight into the structure of the self-assembled switching region. The devices exhibit combined threshold-memory behaviour after an initial voltage-controlled forming process, but exhibit symmetric threshold switching when the RESET and SET currents are kept below a critical value. In this mode, the threshold and hold voltages are shown to be independent of the device area and film thickness, and the threshold power, while independent of device area, is shown to decrease with increasing film thickness. These results are shown to be consistent with a structure in which the threshold switching volume is confined, both laterally and vertically, to the region between the residual memory filament and the electrode, and where the memory filament has a core-shell structure comprising a metallic core and a semiconducting shell. The veracity of this structure is demonstrated by comparing experimental results with the predictions of a resistor network model, and detailed finite element simulations. The next study focuses on electrical self-oscillation of an NbOx threshold switching device incorporated into a Pearson-Anson circuit configuration. Measurements confirm stable operation of the oscillator at source voltages as low as 1.06 V, and demonstrate frequency control in the range from 2.5 to 20.5 MHz with maximum frequency tuning range of 18 MHz/V. The oscillator exhibit three distinct oscillation regimes: sporadic spiking, stable oscillation and damped oscillation. The oscillation frequency, peak-to-peak amplitude and frequency are shown to be temperature and voltage dependent with stable oscillation achieved for temperatures up to ∼380 K. A physics-based threshold switching model with inclusion of device and circuit parameters is shown to explain the oscillation waveform and characteristic. The final study explores the oscillation dynamics of capacitively coupled Nb/Nb2O5 relaxation oscillators. The coupled system exhibits rich collective behaviour, from weak coupling to synchronisation, depending on the negative differential resistance response of the individual devices, the operating voltage and the coupling capacitance. These coupled oscillators are shown to exhibit stable frequency and phase locking states at source voltages as low as 2.2 V with MHz frequency tunable range. The numerical simulation of the coupled system highlights the role of source voltage, and circuit and device capacitance in controlling the coupling modes and dynamics