Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

Design automation algorithms for advanced lithography

In circuit manufacturing, as the technology nodes keep shrinking, conventional 193 nm immersion lithography (193i) has reached its printability limit. To continue the scaling with Moore's law, different kinds of advanced lithography have been proposed, such as multiple patterning lithography (MPL), extreme ultraviolet (EUV), electron beam lithography (EBL) and directed self-assembly (DSA). While these new technologies create enormous opportunities, they also pose great design challenges due to their unique process characteristics and stringent constraints. In order to smoothly adopt these advanced lithography technologies in integrated circuit (IC) fabrication, effective electronic design automation (EDA) algorithms must be designed and integrated into computer-aided design (CAD) tools to address the underlying design constraints and help the circuit designer to better facilitate the lithography process. In this thesis, we focus on algorithmic design and efficient implementation of EDA algorithm for advanced lithography, including directed self-assembly (DSA) and self-aligned double patterning (SADP), to conquer the physical challenges and improve the manufacturing yield. The first advanced lithography technology we explore is self-aligned double patterning (SADP). SADP has the significant advantage over traditional litho-etch-litho-etch (LELE) double patterning in its ability to eliminate overlay, making it a preferable DPL choice for the 14 nm technology node. As in any DPL technology, layout decomposition is the key problem. While the layout decomposition problem for LELE DPL has been well studied in the literature, only a few attempts have been made for the SADP layout decomposition problem. This thesis studies the SADP decomposition problem in different scenarios. SADP has been successfully deployed in 1D patterns and has several applications; however, applying it to 2D patterns turns out to be much more difficult. All previous exact algorithms were based on computationally expensive methods such as SAT or ILP. Other previous algorithms were heuristics without a guarantee that an overlay-free solution can be found even if one exists. The SADP decomposition problem on general 2D layout is proven to be NP-complete. However, we show that if we restrict the overlay, the problem is polynomial-time solvable, and present an exact algorithm to determine if a given 2D layout has a no-overlay SADP decomposition. When designing the layout decomposition algorithms, it is usually useful to take the layout structure into consideration. As most of the current IC layouts adopt a row-based standard cell design style, we can take advantage of its characteristics and design more efficient algorithms compared to the algorithms for general 2D patterns. In particular, the fixed widths of standard cells and power tracks on top and bottom of cells suggest that improvements can be made over the algorithms for general decomposition problem. We present a shortest-path based polynomial time SADP decomposition algorithm for row-based standard cell layout that efficiently finds decompositions with minimum overlay violations. Our proposed algorithm takes advantage of the fixed width of the cells and the alternating power tracks between the rows to limit the possible decompositions and thus achieve high efficiency. The next advanced lithography technology we discuss in the thesis is directed self-assembly (DSA). Block copolymer directed self-assembly (DSA) is a promising technique for patterning contact holes and vias in 7 nm technology nodes. To pattern contacts/vias with DSA, guiding templates are usually printed first with conventional lithography (193i) that has a coarser pitch resolution. Contact holes are then patterned with DSA process. The guiding templates play the role of defining the DSA patterns, which have a finer resolution than the templates. As a result, different patterns can be obtained through controlling the templates. It is shown that DSA lithography is very promising in patterning contacts/vias in 7 nm technology node. However, to utilize DSA for full-chip manufacturing, EDA for DSA must be fully explored because EDA is the key enabler for manufacturing, and the EDA research for DSA is still lagging behind. To pattern the contact layer with DSA, we must ensure that all the contacts in the layout require only feasible DSA templates. Nevertheless, the original layout may not be designed in a DSA-friendly way. However, even with an optimized library, infeasible templates may be introduced after the physical design phase. We propose a simulated-annealing (SA) based scheme to perform full-chip level contact layer optimization. According to the experimental results, the DSA conflicts in the contact layer are reduced by close to 90% on average after applying the proposed optimization algorithm. It is a current trend that industry is transiting from the random 2D designs to highly regular 1D gridded designs for sub-20 nm nodes and fabricating circuit designs with print-cut technology. In this process, the randomly distributed cuts may be too dense to be printed by single patterning lithography. DSA has proven its success in contact hole patterning, and can be easily expanded to cut printing for 1D gridded designs. Nevertheless, the irregular distribution of cuts still presents a great challenge for DSA, as the self-assembly process usually forms regular patterns. As a result, the cut layer must be optimized for the DSA process. To address the above problem, we propose an efficient algorithm to optimize cut layers without hurting the original circuit logic. Our work utilizes a technique called `line-end extension' to move the cuts and extend the functional wires without changing the original functionality of the circuit. Consequently, the cuts can be redistributed and grouped into valid DSA templates. Multiple patterning lithography has been widely adopted for today's circuit manufacturing. However, increasing the number of masks will make the manufacturing process more expensive. By incorporating DSA into the multiple patterning process, it is possible to reduce the number of masks and achieve a cost-effective solution. We study the decomposition problem for the contact layer in row-based standard cell layout with DSA-MP complementary lithography. We explore several heuristic-based approaches, and propose an algorithm that decomposes a standard cell row optimally in polynomial-time. Our experiments show that our algorithm is guaranteed to find a minimum cost solution if one exists, while the heuristic cannot or only finds a sub-optimal solution. Our results show that the DSA-MP complementary approach is very promising for the future advanced nodes. As in any lithography technique, the process variation control and proximity correction are the most important issues. As the DSA templates are patterned by conventional lithography, the patterned templates are prone to deviate from mask shapes due to process variations, which will ultimately affect the contacts after the DSA process even for the same type of template. Therefore, in order to enable the DSA technology in contact/via layer printing, it is extremely important to accurately model and detect hotspots, as well as estimate the contact pitch and locations during the verification phase. We propose a machine learning based design automation framework for DSA verification. A novel DSA model and a set of features are included. We implemented the proposed ML-based flow and performed extensive experiments on comparing the performances of learning algorithms and features. The experimental results show that our approach is much more efficient than the traditional approach, and can produce highly accurate results

EDA Solutions for Double Patterning Lithography

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes

New processing techniques for large-area electronics

Recent advancements in the semiconductor industry have been driven by the extreme downscaling of device dimensions enabled by innovative photolithography methods. However, such nano-scale patterning technologies are impractical for large-area electronics primarily due to extremely high cost and incompatibility with large-area processing. Therefore, alternative techniques that are simpler, more scalable and compatible with large-area manufacturing are required. This thesis explores the technological potential of two recently developed patterning techniques namely interlayer lithography (IL) and adhesion-lithography (a-Lith) for application in the field of large-area nano/electronics. The IL method relies on the use of a pre-patterned metal electrode that acts as the mask during back illumination of a photoresist layer followed by a conventional lift-off process step. On the other hand in the a-Lith approach, the surface energy of a patterned metal electrode is modified through the use of surface energy modifiers such as organic self-assembling monolayer (SAM). Following, a second metal is evaporated on the entire substrate. However, because of the present of the SAM, regions of metal-2 overlapping with metal-1 can easily be peeled off with the aid of an adhesive layer (e.g. sticky tape) leaving behind the two metal electrodes in close proximity to each other. Analysis of the resulting structures reveals that inter-electrode distances <20 nm can easily be achieved. The method was then used to develop innovative process protocols for the fabrication of functional self-aligned gate (SAG) transistor architectures. Best performing devices exhibited charge carrier mobility in the range of 0.5-1 cm2/Vs, high current on-off ratio (~104), negligible operating hysteresis and excellent switching speed. Using the same a-Lith process protocol, low-voltage organic ferroelectric tunnel junction memory devices were also developed by combining the metal-1/metal-2 nanogap electrodes with a ferroelectric copolymer deposited in-between them. Controllable ferroelectric tunnelling was observed enabling the devices’ conductivity to be programmed using low biases and hence been used as a non-volatile memory cell. The alternative and highly scalable patterning methods described in this thesis may one day play a significant role on how largearea electronics of the future would be manufactured.Open Acces

Carbon nanotubes : their synthesis and integration into nanofabricated structures

The field of nanotechnology has experienced constantly increasing interest over the past decades both from industry and academy. Commonly used nanomaterials include: nanoparticles, nanowires, quantum dots, fullerenes, and carbon nanotubes. Carbon nanotubes, in particular, are promising building blocks for a large variety of potential applications. Because of their structure and high aspect ratio, nanotubes have unique electronic, chemical and mechanical properties. These properties attract much interest to the investigation of carbon nanotubes for potential applications in electronics devices, batteries, solar cells, gas storage technologies, and other fields. Topics addressed in this dissertation relate to the synthesis of carbon nanotubes and their integration into different structures, with particular focus on the basic problems of nanofabrication. Chapter 1 discusses the recent developments of the research activity in the field of post-synthesis placement of carbon nanotubes (CNTs) on substrates. This includes alignment guided by physical forces, external fields and chemical interactions. The usefulness of any given technique strongly depends on the desired application, while additional innovations for the further expansion of the post-synthesis alignment field need to be introduced. Chapter 2 introduces the microwave-assisted synthesis of one-dimensional carbon nanostructures. Selective heating of small iron nanoparticles, often used as a catalyst to initiate the growth of CNTs, was investigated under microwave irradiation. An important advantage of this approach is the fact that the heat development is limited to the close vicinity of the nanoparticles, while the average overall temperature in the reaction vial remains low, allowing the utilization of a diverse range of substrate materials. The approach to synthesize carbon nanofibers (CNFs) and nanotubes was adapted to the special requirements of the microwave apparatus and had to be optimized for safety. By using ethanol as a carbon source, provided by a liquid reservoir located beneath the sample, a flux of highly flammable and explosive gas mixtures was avoided. The reaction conditions for the microwave-assisted synthesis of carbon nanotubes and nanofibers were investigated in detail. These were observed to have a strong influence on the CNT/CNF formation and on the quality of the obtained materials. Further improvement of the quality and size of the synthesized materials was obtained by variation of the catalyst material. Nickel was identified as the most favorable catalyst material to obtain small nanotube diameters down to 15 nm using very short irradiation times of two minutes. Compensation of the heat dissipation, for substrates showing a low absorption of microwave irradiation (mica and quartz glass), resulted in reliable processes that enable the microwave-assisted growth of CNTs on a variety of substrates. It was demonstrated that the growth of individual CNTs can be achieved. In particular, the relatively low experimental effort, as well as the fast fabrication times, are general advantages of this method and provide a promising, cheap technique to fabricate CNT-modified AFM tips. The deposition of the catalyst material can be further improved by, e.g., utilizing particle picking approaches or by force versus distance curve recording, to further increase the controllability of the presented approach. Results show that small areas can be covered with a suitable catalyst layer with this method. This permits the growth of individual CNTs, as opposed to bundles, and has important implications for the effective integration of carbon nanomaterials into the framework of devices. Carbon nanotubes were successfully grown on micro- and nanoscale patterned areas. These findings are expected to have an additional impact on the use of the selective heating mechanism, as it provides advantages over conventional methods, i.e., the reduced reaction time, the lower overall exposure temperature to the substrates and for the integration of CNTs/CNFs into predefined device frameworks consisting of different materials. Chapter 3 gives a comprehensive overview of the electro-oxidation lithography on chemically active surfaces. This powerful technique can be used to organize nanomaterials into defined structures. The main advantage of this technique is the fact that it can manipulate and guide the position of catalyst particles, nanowires or other nanometer-scale objects that are required for the desired structures. Due to the fact that addressable functional groups are created during the electrochemical oxidation, it is possible to utilize the entire range of intermolecular interactions to modify the structures. These include electrostatic and van der Waals interactions, hydrogen bonding, covalent bonding and complexation reactions to selectively bind suitable building blocks. This approach can also be used for the post-synthesis organization of carbon nanotubes and, moreover, provides unique possibilities for the fabrication of nanomaterials. Chapter 4 discusses the post-synthesis assembly of carbon nanotubes of the pre-patterned structures. Stable suspensions of carbon nanotubes were prepared via several different approaches, including agitation in organic solvents or the use of surfactants. The latter yielded in stable suspensions of carbon nanotubes. Electro-chemical oxidation lithography was utilized for the placement of individual carbon nanotubes. The structuring of the n-octadecyltrichlorosilane (OTS) monolayer was repeated and, in a second oxidation process, new active binding sites were generated. This was followed by the sequential placement of CNTs onto chemically active surface templates created in the vicinity of the existing tube. Major advantages of this approach include good control over the lateral placement of the CNTs and the availability of addressable chemical functional surface templates. Furthermore, the possibility to preselect the self-assembling building blocks as well as the sequential nature of the patterning process are discussed, which are not easily accessible by conventional lithographic tools, i.e., photo- and e-beam lithography. This process provides the possibility to carefully select the tube material and to combine pre-defined building blocks, e.g. in transistor layouts. Thus, a powerful approach has been developed that allows control over the device layout at several length scales. Chapter 5 demonstrates two new concepts for the use of electro-oxidative lithography for the formation of nanoscale building blocks, e.g., nanometer gaps and metallic circles as shown in this work. The electro-chemical oxidation of monolayers and bilayers consisting of OTS was investigated in detail, including the different oxidation times required to perform the electrochemical oxidation on monolayer and bilayer systems. Thus, a new rational design to generate well-defined gap-structures was established. In particular, the fabrication of a nanometric gap structure and an approach to assemble a nanoelectronic-based device layout was developed. The second concept introduces a new fabrication method to obtain ring structures with nanometer dimensions. This method combines the silicon growth mode and the monolayer oxidation mode from the available electro-oxidation lithography techniques. The oxidation conditions, as well as the scaling options of this lithographic process were investigated and revealed good controllability of the feature dimensions. These structures were further functionalized with silver particles, thus, converting the structure into mesoscopic ring structures with sufficiently high uniformity and reproducible quality. These concepts can be used for the formation of nano-scale functional devices. In conclusion, new concepts have been developed to target different, challenging aspects of nanofabrication. This combines alternative synthesis strategies for carbon nanotubes and the implementation of these nanotubes into nanostructures. Electro-oxidative lithography was utilized as a chemical structuring tool to guide self-assembly processes of nanotubes and nanoparticles. Fundamental investigations on the oxidation conditions allowed a significant expansion of the applicability of this structuring technique and demonstrated the possibility to target different aspects of modern nanofabrication

Graphene transistors for radio frequency applications

Dissertação de mestrado integrado em Engenharia Física (área de especialização em Dispositivos, Microssistemas e Nanotecnologias)O grafeno atraiu imensa atenção devido à alta mobilidade dos portadores de carga, tornando um potencial novo material para eletrónica de radio frequência. Transístores fabricados com grafeno, fabricados até à data, possuem frequência de corte intrínsecas de 427 GHz. O fabrico de transístores de grafeno para aplicações de radiofrequência é dificultado devido às tecnologias de fabrico CMOS não poderem ser usadas, no seu estado atual, para este novo material. Neste trabalho, uma deposição física da porta e do óxido da porta foi escolhida de forma a minimizar os danos causados à rede de grafeno e um processo de auto alinhamento para reduzir as resistências de contacto. De forma a maximizar as figuras de mérito das estruturas pretendidas, foram feitas simulações que correlacionam os parâmetros físicos do dispositivo com as figuras de mérito. Os resultados obtidos dessas simulações mostraram que a elevada discrepância entre as figuras de mérito intrínsecas e extrínsecas resultam do elevado rácio entre as capacitâncias da porta dreno e porta-fonte para as capacitâncias parasíticas da porta e do dreno. Um aumento da camada de passivação e redução dos pads resultam na redução significativa do rácio entre os dois. As simulações também mostraram que reduzindo as resistências, capacidades e indutâncias parasitas resulta numa melhoria das figuras de mérito. A redução da largura do canal e aumento do comprimento do canal resulta no aumento das figuras de mérito intrínsecas e consequentemente as extrínsecas. O grafeno foi crescido por CVD numa folha de cobre, que produz alta qualidade e grandes áreas, e transferido para um substrato isolador. Nano-fios de níquel foram crescidos por deposição eletroquímica usando estruturas de oxido de alumínio anodizado (AAO) com uma camada de semente fina de ouro e uma mistura de NiSO4, NiCl2 e H3BO3, produziram nano-fios com diâmetros entre 200 e 400 nm. A estrutura foi removida com uma solução de NaOH, expondo os nano-fios. A cobertura dos nano-fios foi realizada através da oxidação do níquel e deposição de dióxido de silício. Ambas estas estruturas de núcleo-concha foram utilizadas na fabricação dos transístores. Os nano-fios núcleo-concha foram libertados da camada semente com uma solução de KI e I2, e subsequentemente aleatoriamente posicionados em cima do grafeno. Imagens de alta resolução foram obtidas da exata posição dos nano-fios e com a ajuda de marcadores de Titânio- Tungstênio (TiW), previamente depositados, mascaras para os processos litográficos foram desenhadas, estabelecendo um comprimento do canal em 3 μm. O processo de auto alinhamento foi por fim usado para depositar os contactos do dreno e fonte (Cr/Pd), alinhando-os perfeitamente e reduzindo a resistência de contacto por consequência. Um processo dieletroforético foi também desenvolvido para posicionar precisamente os nano-fios no substrato e possibilitar a escalabilidade do processo de fabrico. Por último, caracterização dos dispositivos fabricados foi realizada. Os dispositivos fabricados na primeira iteração mostraram baixo isolamento entre a porta e o canal, sendo esta atribuída ao dielétrico escolhido. Os dispositivos da segunda iteração do processo de fabrico foram impossíveis de caracterizar eletricamente devido à falta de conexão elétrica após a primeira ligação das sondas de medição.Graphene has attracted an immense amount of attention due to its high carrier mobility, making it a potentially new material for radio-frequency electronics. Transistors fabricated with graphene have reached intrinsic cut-off frequencies of 300 GHz. The fabrication of graphene RF transistors is challenging as most of the standard CMOS technologies cannot be employed in their current state to this new material. In this work, a physical deposition of the gate and gate oxide was chosen to minimize the damages to the graphene lattice and a self-aligned process to reduce the contact resistance. In order to maximize the figures of merit of the intended structure, simulations were made correlating the physical parameters to the figures of merit. Results obtained from these simulations showed that the high discrepancy between intrinsic and extrinsic figures of merit resulted from the high ratio between the gate-drain and gate-source capacitances to the parasitic gate and drain parasitic capacitances. An increase in the passivation layer and reduction of the gate and drain pads results in a significantly lower ratio between the two. Simulations also showed that, by minimizing the parasitic resistances, capacitances and inductances results in the increase of both intrinsic and extrinsic figures of merit. Reduction of the channel length and increase of the channel width results in the increase of the intrinsic, and subsequently extrinsic, figures of merit. Graphene was grown by CVD on a copper foil, which yielded high quality and large area graphene, and transferred onto the insulating substrate. Nickel nanowires were grown by electrochemical deposition using an Anodized Aluminum Oxide (AAO) template with a gold seed layer and a mixture of NiSO4, NiCl2 and H3BO3, resulting in nanowires with diameters ranging from 200 to 400 nanometers. The template was removed with a solution of NaOH creating free standing nanowires. Coating of the nanowires was performed through the oxidation of nickel and deposition of silicon dioxide. Both of these types of core-shell nanowires were used in the fabrication of the transistors. The core-shell nanowires were released from the seed layer with a solution of KI and I2 and subsequently randomly placed on top of the graphene. High resolution images of the nanowires precise position were taken and with the aid of Titanium-Tungsten (TiW) markers previously deposited, masks for a lithographic process were designed, setting the channel width to 3 μm. A self-aligned process was lastly employed to deposit the Drain-Source contacts (Cr/Pd), perfectly aligning them and in turn, greatly reducing the access resistance. A dielectrophoretic method was also developed to perfectly position the nanowires on the substrate and in turn scale up the device fabrication process. Lastly, characterization of the fabrication took place. Devices fabricated on the first run of the experiment showed poor isolation between the gate and channel of the devices. This was attributed to the dielectric choice. The second set of fabricated devices were unable to be characterized as connections made onto the devices failed to provide electrical contact after the first placement of the measuring probes

Algorithms for DFM in electronic design automation

As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit of physics at the expense of design flexibility. On the other hand, IC designs inevitably becomes more complex to meet the increasing demand of computational power. To close this gap, design for manufacturing (DFM) becomes the key to enable an easy and low-cost IC fabrication. Therefore, efficient electronic design automation (EDA) algorithms must be developed for DFM to address the design constraints and help the designers to better facilitate the manufacture process. As the core of manufacturing ICs, conventional lithography systems (193i) reach their limit for the 22 nm technology node and beyond. Consequently, several advanced lithography techniques are proposed, such as multiple patterning lithography (MPL), extreme ultra-violet lithography (EUV), electron beam (E-beam), and block copolymer directed self-assembly (DSA); however, DFM algorithms are essential for them to achieve better printability of a design. In this dissertation, we focus on analyzing the compatibility of designs and various advanced lithography techniques, and develop efficient algorithms to enable the manufacturing. We first explore E-Beam, one of the promising candidates for IC fabrication beyond the 10 nm technology node. To address its low throughput issue, the character projection technique has been proposed, and its stencil planning can be optimized with an awareness of overlapping characters. 2D stencil planning is proved NP-Hard. With the assumption of standard cells, the 2D problem can be partitioned into 1D row ordering subproblems; however, it is also considered hard, and no efficient optimal solution has been provided so far. We propose a polynomial time optimal algorithm to solve the 1D row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Technical proofs and experimental results verify that our algorithm is efficient and indeed optimal. As the most popular and practical lithography technique, MPL utilizes multiple exposures to print a single layout and thus allows placement of features within the minimum distance. Therefore, a feasible decomposition of the layout is a must to adopt MPL, and it is usually formulated as a graph k-coloring problem, which is computationally difficult for k > 2. We study the k-colorability of rectangular and diagonal grid graphs as induced subgraphs of a rectangular or diagonal grid respectively, since it has direct applications in printing contact/via layouts. It remains an open question on how hard it is to color grid graphs due to their regularity and sparsity. In this dissertation, we conduct a complete analysis of the k-coloring problems on rectangular and diagonal grid graphs, and particularly the NP-completeness of 3-coloring on a diagonal grid graph is proved. In practice, we propose an exact 3-coloring algorithm for those graphs and conduct experiments to verify its performance and effectiveness. Besides, we also develop an efficient algorithm for model based MPL, because it is more expensive but accurate than the rule based decomposition. As one of the alternative lithography techniques, block copolymer directed self-assembly (DSA) is studied. It has emerged as a low-cost, high- throughput option in the pursuit of alternatives to traditional optical lithography. However, issues of defectivity have hampered DSA’s viability for large-scale patterning. Recent studies have shown the copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density has been demonstrated. In this dissertation, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. We also apply our knowledge in coloring grid graphs to the problem of group-and-coloring in DSA-MPL hybrid lithography. We derive a solution to group-3-coloring and prove the NP-completeness of grouping-2-coloring

Standard cell optimization and physical design in advanced technology nodes

Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor technology is IC feature-size miniaturization. However, this brings ever-increasing design complexities and manufacturing challenges to the $340 billion semiconductor industry. The manufacturing of two-dimensional layout on high-density metal layers depends on complex design-for-manufacturing techniques and sophisticated empirical optimizations, which introduces huge amounts of turnaround time and yield loss in advanced technology nodes. Our study reveals that unidirectional layout design can significantly reduce the manufacturing complexities and improve the yield, which is becoming increasingly adopted in semiconductor industry [61, 89]. The lithography printing of unidirectional layout can be tightly controlled using advanced patterning techniques, such as self-aligned double and quadruple patterning. Despite the manufacturing benefits, unidirectional layout leads to more restrictive solution space and brings significant impacts on the IC design automation ow for routing closure. Notably, unidirectional routing limits the standard cell pin accessibility, which further exacerbates the resource competitions during routing. Moreover, for post-routing optimization, traditional redundant-via insertion has become obsolete under unidirectional routing style, which makes the yield enhancement task extremely challenging. Regardless of complex multiple patterning and design-for-manufacturing approaches, mask optimization through resolution enhancement techniques remains as the key strategy to improve the yield of the semiconductor manufacturing processes. Among them, Sub-Resolution Assist Feature (SRAF) generation is a very important method to improve lithographic process windows. Model-based SRAF generation has been widely used to achieve high accuracy but it is time-consuming and hard to obtain consistent SRAFs. This dissertation proposes novel CAD algorithms and methodologies for standard cell optimization and physical design in advanced technology nodes, which ultimately reduces the design cycle and manufacturing cost of IC design. First, a standard cell pin access optimization engine is proposed to evaluate the pin accessibility of a given standard cell library. We further propose novel pin access planning techniques and concurrent pin access optimizations to efficiently resolve the routing resource competitions, which generates much better routing solutions than state-of-the-art, manufacturing-friendly routers. To systematically improve the manufacturing yield in the post-routing stage, a global optimization engine has been introduced for redundant local-loop insertion considering advanced manufacturing constraints. Finally, we propose the first machine learning-based framework for fast yet consistent SRAF generation with the high quality of results.Electrical and Computer Engineerin

Application Of Nano-Imprint Lithography For Next Generation Carbon Nanotube-Based Devices

This research report addresses the development of 3D carbon nanostructures that can provide unique capabilities for manufacturing carbon nanotube (CNT) electronic components, electrochemical probes, biosensors and tissue scaffolds. The shaped CNT arrays were grown on patterned catalytic substrate by chemical vapor deposition (CVD) method. The new fabrication process for catalyst patterning based on combination of nano-imprint lithography (NIL), magnetron sputtering and reactive etching techniques was proposed and studied. The optimal process parameters for each technique were evaluated. The catalyst was made by deposition of Fe and Co nanoparticles over alumina support layer on Si/SiO2 substrate. The metal particles were deposited using direct current (DC) magnetron sputtering technique, with the particles size from 6 nm to 12 nm and density from 70 to 1000 particles/micron2. Alumina layer was deposited by radio frequency (RF) and reactive pulsed DC sputtering, and the effect of sputtering parameters on surface roughness was studied. The pattern was developed by thermal NIL using Si master-molds and PMMA and NRX1025 polymers as a thermal resists. Catalyst patterns of lines, dots and holes ranging from 70 nm to 500 nm were produced and characterized by scanning electron microscopy (SEM) and atomic force microscopies (AFM). Vertically aligned CNTs were successfully grown on patterned catalyst and their quality was evaluated by SEM and micro-Raman. The results confirm that the new fabrication process has ability to control the size and shape of CNT arrays without loss of their quality