Hardware Design of Digital System with Remote-DiagnosticCapability

In this paper, a hardware design of digital systems with remote-diagnostic capability is presented. We consider a method for testing a system T(l) on a module basis with a remotely installed systems T(2). In the testing mode, we set up a system (T(l)-m,m') such that a module m of T(l) is replaced by an adapter A(1) connected to other adapter A(2) through a telephone line and the corresponding module m' of T(2) is connected to A(2). If the system (T(l)-m,m') can simulate T(1) in the absence of any faluts, then it can test m' under a self test program. The main subject of this paper is to study the conditions of the system to be testable in the above sense. At first, the remote diagnostic network based on the system in this paper, restrictions to the system configuration required to perform such a diagnosis and the operation of the diagnostic system are described. The second, the module structure to make above simulation possible is considered, representing the system configuration graphically. Finally, an example of the adapter is shown and the time consumed to diagnose is discussed. One of our results is that a sufficiently large class of synchronous digital systems with few minor conventions is testable

A self-timed multipurpose delay sensor for field programmable gate arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor’s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration

Elasticity and Petri nets

Digital electronic systems typically use synchronous clocks and primarily assume fixed duration of their operations to simplify the design process. Time elastic systems can be constructed either by replacing the clock with communication handshakes (asynchronous version) or by augmenting the clock with a synchronous version of a handshake (synchronous version). Time elastic systems can tolerate static and dynamic changes in delays (asynchronous case) or latencies (synchronous case) of operations that can be used for modularity, ease of reuse and better power-delay trade-off. This paper describes methods for the modeling, performance analysis and optimization of elastic systems using Marked Graphs and their extensions capable of describing behavior with early evaluation. The paper uses synchronous elastic systems (aka latency-tolerant systems) for illustrating the use of Petri nets, however, most of the methods can be applied without changes (except changing the delay model associated with events of the system) to asynchronous elastic systems.Peer ReviewedPostprint (author's final draft